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[Xen-devel] [PATCH v3 00/18] x86emul: MMX/SSEn support

This includes support for AVX counterparts of them as well as a few
later SSE additions (basically covering the entire 0f-prefixed opcode
space, but not the 0f38 and 0f3a ones, nor 3dnow).

 1: catch exceptions occurring in stubs
 2: support most memory accessing MMX/SSE{,2,3} insns
 3: support MMX/SSE/SSE2 moves
 4: support MMX/SSE/SSE2 converts
 5: support {,V}{,U}COMIS{S,D}
 6: support MMX/SSE/SSE2 insns with only register operands
 7: support {,V}{LD,ST}MXCSR
 8: support {,V}MOVNTDQA
 9: test: split generic and testcase specific parts
10: test coverage for SSE/SSE2 insns
11: honor MMXEXT feature flag
12: add tables for 0f38 and 0f3a extension space

Partly RFC from here on, as there's testing code still mostly missing.

13: support SSSE3 insns
14: support SSE4.1 insns
15: support SSE4.2 insns
16: support PCLMULQDQ
17: support AESNI insns
18: support SHA insns

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
v3: New patches 11-18. Fixes in other patches see there.

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