Re: [Xen-devel] [PATCH 09/19] x86/vmce: fill MSR_IA32_MCG_STATUS on all vcpus in broadcast case

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 20.02.17 at 05:36, <haozhong.zhang@xxxxxxxxx> wrote:
> On 02/17/17 03:21 -0700, Jan Beulich wrote:
>> >>> On 17.02.17 at 07:39, <haozhong.zhang@xxxxxxxxx> wrote:
>> > +            continue;
>> > +        ret = vcpu_fill_mc_msrs(v, MCG_STATUS_MCIP | MCG_STATUS_RIPV,
>> > +                                0, 0, 0);
>> 
>> What guarantees RIP to be valid, and why all the zeros? Perhaps
>> I'm lacking some understanding of how real hardware handles the
>> broadcasting, but it would help if you left an explaining comment
>> here.
>>
> 
> I just inject the less severity error on vcpus other than vcpu0. As
> long as vMCE with the actual error information is injected to vcpu0,
> the guest MCE handler should be able to decide whether it can recover
> or not. If it can, vMCE injected on other vcpus should not offer
> conflict information. If it cannot, MC MSRs on other vcpus will not
> matter in fact as they represent a less severe error.
> 
> MSR_IA32_MCG_STATUS = MCG_STATUS_MCIP | MCG_STATUS_RIPV and all banks
> being zero (invalid) is one of the combinations satisfying above
> requirement.

Well, okay, but as said - this needs saying in a code comment.

Jan


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