Re: [Xen-devel] [PATCH 02/10] x86/gen-cpuid: Clarify the intended meaning of AVX wrt feature dependencies

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

On 21/02/17 16:40, Jan Beulich wrote:
>>>> On 20.02.17 at 12:00, <andrew.cooper3@xxxxxxxxxx> wrote:
>> --- a/xen/tools/gen-cpuid.py
>> +++ b/xen/tools/gen-cpuid.py
>> @@ -225,9 +225,13 @@ def crunch_numbers(state):
>>          XSAVE: [XSAVEOPT, XSAVEC, XGETBV1, XSAVES,
>>                  AVX, MPX, PKU, LWP],
>>  
>> -        # AVX is taken to mean hardware support for VEX encoded 
>> instructions,
>> -        # 256bit registers, and the instructions themselves.  Each of these
>> -        # subsequent instruction groups may only be VEX encoded.
>> +        # AVX is taken to mean hardware support for 256bit registers (which 
>> in
>> +        # practice depends on the VEX prefix to encode), and the 
>> instructions
>> +        # themselves.
>> +        #
>> +        # AVX is not taken to mean support for the VEX prefix itself.
>> +        # VEX-encoded GPR instructions, such as those from the BMI{1,2} sets
>> +        # function fine in the absence of any enabled xstate.
>>          AVX: [FMA, FMA4, F16C, AVX2, XOP],
> Even if there aren't any EVEX-encoded non-AVX512 instructions so
> far, I'd prefer the AVX512F entry to get adjusted along the same
> lines.

Good point.  I will update.

> With that Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>

Thanks,

~Andrew

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