Re: [Xen-devel] [PATCH v3 3/3] x86/vmx: fix vmentry failure with TSX bits in LBR

["Tian, Kevin" <kevin.tian@xxxxxxxxx>]

> From: Sergey Dyasli [mailto:sergey.dyasli@xxxxxxxxxx]
> Sent: Thursday, February 23, 2017 5:33 PM
> 
> During VM entry, H/W will automatically load guest's MSRs from MSR-load
> area in the same way as they would be written by WRMSR.
> 
> However, under the following conditions:
> 
>     1. LBR (Last Branch Record) MSRs were placed in the MSR-load area
>     2. Address format of LBR includes TSX bits 61:62
>     3. CPU has TSX support disabled
> 
> VM entry will fail with a message in the log similar to:
> 
>     (XEN) [   97.239514] d1v0 vmentry failure (reason 0x80000022): MSR 
> loading (entry
> 3)
>     (XEN) [   97.239516]   msr 00000680 val 1fff800000102e60 (mbz 0)
> 
> This happens because of the following behaviour:
> 
>     - When capturing branches, LBR H/W will always clear bits 61:62
>       regardless of the sign extension
>     - For WRMSR, bits 61:62 are considered the part of the sign extension
> 
> This bug affects only certain pCPUs (e.g. Haswell) with vCPUs that
> use LBR.  Fix it by sign-extending TSX bits in all LBR entries during
> VM entry in affected cases.
> 
> LBR MSRs are currently not Live Migrated. In order to implement such
> functionality, the MSR levelling work has to be done first because
> hosts can have different LBR formats.
> 
> Signed-off-by: Sergey Dyasli <sergey.dyasli@xxxxxxxxxx>

Acked-by: Kevin Tian <kevin.tian@xxxxxxxxx>

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