[Xen-devel] [PATCH 3/3] x86/vlapic: Reset LAPIC Timer only on TSC Deadline mode change

[Anthony PERARD <anthony.perard@xxxxxxxxxx>]

For the LAPIC timer, switching between periodic and one-shot does not
reset anything on real-hardward, but switching from TSC deadline or to
it does reset the timer, according to Intel manual.

Signed-off-by: Anthony PERARD <anthony.perard@xxxxxxxxxx>

---
I'm not sure that TMICT should be reset, but the manuel said that in
tsc-deadline, write to TMICT are ignored.
---
 xen/arch/x86/hvm/vlapic.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
index f70a25f5b9..18247bd8bb 100644
--- a/xen/arch/x86/hvm/vlapic.c
+++ b/xen/arch/x86/hvm/vlapic.c
@@ -839,9 +839,11 @@ static void vlapic_reg_write(struct vcpu *v,
         break;
 
     case APIC_LVTT:         /* LVT Timer Reg */
-        if ( (vlapic_get_reg(vlapic, offset) & APIC_TIMER_MODE_MASK) !=
-             (val & APIC_TIMER_MODE_MASK) )
+        /* Switching between tdt and periodic|one-shot reset the other mode */
+        if ( vlapic_lvtt_tdt(vlapic) !=
+             ((val & APIC_TIMER_MODE_MASK) == APIC_TIMER_MODE_TSC_DEADLINE))
         {
+            vlapic_set_reg(vlapic, APIC_TMICT, 0);
             vlapic->hw.tdt_msr = 0;
         }
         vlapic->pt.irq = val & APIC_VECTOR_MASK;
-- 
Anthony PERARD


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