Re: [Xen-devel] Question about the general performance counter overflow interrupt handling

[Meng Xu <mengxu@xxxxxxxxxxxxxx>]

Hi Boris,

On Fri, Mar 31, 2017 at 12:01 PM, Boris Ostrovsky
<boris.ostrovsky@xxxxxxxxxx> wrote:
>
>>> When I program the general performance counter to trigger an overflow
>>> interrupt, I set the following bits for the event selector register
>>> and run a task to generate the L3 cache cache miss.
>>> FLAG_ENABLE: 0x400000UL
>>> FLAG_INT:    0x100000UL
>>> FLAG_USR: 0x010000UL
>>> L3_ALLMISS_EVENT    0x2E
>>> L3_ALLMISS_MESI     0x41
>>>
>>> I'm sure the performance counter does overflow, but I didn't see any
>>> interrupt was triggered. Maybe I missed something?
>
> Did you program global registrers (MSR_CORE_PERF_GLOBAL_CTRL,
> MSR_CORE_PERF_GLOBAL_OVF_CTRL)?

I tried two scenarios:
Scenario1)
    MSR_CORE_PERF_GLOBAL_CTRL (0x38F) = 0x0
    MSR_CORE_PERF_GLOBAL_OVF_CTRL (0x390) = 0x0
    The function pmu_apic_interrupt() is not called.
Scenario 2)
   MSR_CORE_PERF_GLOBAL_CTRL (0x38F) = 0xff
    MSR_CORE_PERF_GLOBAL_OVF_CTRL (0x390) = 0x0
    The function pmu_apic_interrupt() is not called either.

In both scenarios, the IA32_PERF_GLOBAL_STATUS (0x38E) is 0xf.

I tried to set MSR_CORE_PERF_GLOBAL_OVF_CTRL to 0xf, but the
register's content is not changed. :(

Maybe I should set the MSR_CORE_PERF_GLOBAL_OVF_CTRL to 0xF to enable
the overflow interrupt?

Thank you very much for your time and help!

Meng

-----------
Meng Xu
PhD Candidate in Computer and Information Science
University of Pennsylvania
http://www.cis.upenn.edu/~mengxu/

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