Re: [Xen-devel] [PATCH v3 10/16] xen/arm: lpae: Fix comments coding style

[Sergej Proskurin <proskurin@xxxxxxxxxxxxx>]

Hi Julien,

On 06/30/2017 05:54 PM, Julien Grall wrote:
> Also adding one missing full stop + fix description
> 
> Signed-off-by: Julien Grall <julien.grall@xxxxxxx>
> Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
> ---
> 
> Cc: proskurin@xxxxxxxxxxxxx
> 
>     I haven't retained Stefano's reviewed-by because of the description
>     update.
> 
>    Changes in v2:
>         - Fix description regarding x86 page-table
> 
>     Changes in v3:
>         - Add Stefano's reviewed-by


Reviewed-by: Sergej Proskurin <proskurin@xxxxxxxxxxxxx>


> ---
>  xen/include/asm-arm/lpae.h | 49 
> ++++++++++++++++++++++++++++++----------------
>  1 file changed, 32 insertions(+), 17 deletions(-)
> 
> diff --git a/xen/include/asm-arm/lpae.h b/xen/include/asm-arm/lpae.h
> index ad8c571ea5..aa85cb8112 100644
> --- a/xen/include/asm-arm/lpae.h
> +++ b/xen/include/asm-arm/lpae.h
> @@ -3,10 +3,12 @@
>  
>  #ifndef __ASSEMBLY__
>  
> -/* WARNING!  Unlike the Intel pagetable code, where l1 is the lowest
> - * level and l4 is the root of the trie, the ARM pagetables follow ARM's
> - * documentation: the levels are called first, second &c in the order
> - * that the MMU walks them (i.e. "first" is the root of the trie). */
> +/*
> + * WARNING!  Unlike the x86 pagetable code, where l1 is the lowest level and
> + * l4 is the root of the trie, the ARM pagetables follow ARM's documentation:
> + * the levels are called first, second &c in the order that the MMU walks 
> them
> + * (i.e. "first" is the root of the trie).
> + */
>  
>  
> /******************************************************************************
>   * ARMv7-A LPAE pagetables: 3-level trie, mapping 40-bit input to
> @@ -17,15 +19,18 @@
>   * different place from those in leaf nodes seems to be to allow linear
>   * pagetable tricks.  If we're not doing that then the set of permission
>   * bits that's not in use in a given node type can be used as
> - * extra software-defined bits. */
> + * extra software-defined bits.
> + */
>  
>  typedef struct __packed {
>      /* These are used in all kinds of entry. */
>      unsigned long valid:1;      /* Valid mapping */
>      unsigned long table:1;      /* == 1 in 4k map entries too */
>  
> -    /* These ten bits are only used in Block entries and are ignored
> -     * in Table entries. */
> +    /*
> +     * These ten bits are only used in Block entries and are ignored
> +     * in Table entries.
> +     */
>      unsigned long ai:3;         /* Attribute Index */
>      unsigned long ns:1;         /* Not-Secure */
>      unsigned long user:1;       /* User-visible */
> @@ -38,30 +43,38 @@ typedef struct __packed {
>      unsigned long long base:36; /* Base address of block or next table */
>      unsigned long sbz:4;        /* Must be zero */
>  
> -    /* These seven bits are only used in Block entries and are ignored
> -     * in Table entries. */
> +    /*
> +     * These seven bits are only used in Block entries and are ignored
> +     * in Table entries.
> +     */
>      unsigned long contig:1;     /* In a block of 16 contiguous entries */
>      unsigned long pxn:1;        /* Privileged-XN */
>      unsigned long xn:1;         /* eXecute-Never */
>      unsigned long avail:4;      /* Ignored by hardware */
>  
> -    /* These 5 bits are only used in Table entries and are ignored in
> -     * Block entries */
> +    /*
> +     * These 5 bits are only used in Table entries and are ignored in
> +     * Block entries.
> +     */
>      unsigned long pxnt:1;       /* Privileged-XN */
>      unsigned long xnt:1;        /* eXecute-Never */
>      unsigned long apt:2;        /* Access Permissions */
>      unsigned long nst:1;        /* Not-Secure */
>  } lpae_pt_t;
>  
> -/* The p2m tables have almost the same layout, but some of the permission
> - * and cache-control bits are laid out differently (or missing) */
> +/*
> + * The p2m tables have almost the same layout, but some of the permission
> + * and cache-control bits are laid out differently (or missing).
> + */
>  typedef struct __packed {
>      /* These are used in all kinds of entry. */
>      unsigned long valid:1;      /* Valid mapping */
>      unsigned long table:1;      /* == 1 in 4k map entries too */
>  
> -    /* These ten bits are only used in Block entries and are ignored
> -     * in Table entries. */
> +    /*
> +     * These ten bits are only used in Block entries and are ignored
> +     * in Table entries.
> +     */
>      unsigned long mattr:4;      /* Memory Attributes */
>      unsigned long read:1;       /* Read access */
>      unsigned long write:1;      /* Write access */
> @@ -73,8 +86,10 @@ typedef struct __packed {
>      unsigned long long base:36; /* Base address of block or next table */
>      unsigned long sbz3:4;
>  
> -    /* These seven bits are only used in Block entries and are ignored
> -     * in Table entries. */
> +    /*
> +     * These seven bits are only used in Block entries and are ignored
> +     * in Table entries.
> +     */
>      unsigned long contig:1;     /* In a block of 16 contiguous entries */
>      unsigned long sbz2:1;
>      unsigned long xn:1;         /* eXecute-Never */
> 

-- 
Sergej Proskurin, M.Sc.
Wissenschaftlicher Mitarbeiter

Technische Universität München
Fakultät für Informatik
Lehrstuhl für Sicherheit in der Informatik

Boltzmannstraße 3
85748 Garching (bei München)

Tel. +49 (0)89 289-18592
Fax +49 (0)89 289-18579

proskurin@xxxxxxxxxxxxx
www.sec.in.tum.de

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