Re: [Xen-devel] xen/arm: Software Step ARMv8 - PC stuck on instruction

[Julien Grall <julien.grall@xxxxxxx>]

On 07/04/2017 01:30 PM, Florian Jakobsmeier wrote:
> Hello all,
Hi Florian,

>       asmlinkage void leave_hypervisor_tail(void)
>       {
>     +    /*This methode will be called after the 'guest_entry' macro in
>     /arch/arm64/entry.S set guest registers
>     +    Check single_step_enabled flag in domain struct here and set
>     needed registers
>     +
>     +    */
>     +
>     +    struct vcpu *v = current;
>     +
>     +    if ( unlikely(v->domain->arch.monitor.singlestep_enabled ) )
>     +    {
>     +
>     +        WRITE_SYSREG(READ_SYSREG(MDCR_EL2)  | HDCR_TDE, MDCR_EL2);
>     +        WRITE_SYSREG(READ_SYSREG(SPSR_EL2)  | 0x200000, SPSR_EL2 );
>     +        WRITE_SYSREG(READ_SYSREG(MDSCR_EL1) | 0x1, MDSCR_EL1);
>     +
>     +        if (!(v->arch.single_step ))
>     +        {
>     +            gprintk(XENLOG_ERR, "Setting vcpu=%d for
>     domain=%d\n",v->vcpu_id,v->domain->domain_id);
>     +
>     +            gprintk(XENLOG_ERR, "[Set_singlestep] MDSCR_EL1    
>     0x%lx\n", READ_SYSREG(MDSCR_EL1));
>     +            gprintk(XENLOG_ERR, "[Set_singlestep] SPSR_EL2     
>     0x%lx\n", READ_SYSREG(SPSR_EL2));
>     +            gprintk(XENLOG_ERR, "[Set_singlestep] MDCR_EL2     
>     0x%lx\n", READ_SYSREG(MDCR_EL2));
>     +            v->arch.single_step = 1;
>     +
>     +            return;
>     +        }else
>     +        {
>     +            //gprintk(XENLOG_ERR, "Register for vcpu=%d for
>     domain=%d already set\n",v->vcpu_id,v->domain->domain_id);
>     +        }
>     +    }
>
>
> As mentioned, this function will set the needed registers. 
> "monitor.singlestep_enabled" is the domain SS flag which is used to 
> determine if the registers should be set. "arch.single_step" is the vcpu 
> flag to check if the register were already set once (not really in use 
> as for now). "HDCR_TDE" is the same value as "MDCR_EL2_TDE" would be, 
> but this one is not implemented yet, thats why I'm using HDCR_TDE. 
> "SPSR_EL2 | 0x200000" sets the SS bit for EL2 (because our exception 
> will be taken to the hypervisor). "MDSCR_EL1 | 0x1" to enable the SS bit.
> Because I'm checking the domain in this function, every vcpu that will 
> be used, will be set with the values above. By this I can assure that 
> each vcpu will trigger these exceptions.
SPSR_EL2 is saved/restored on entry and exit of a trap to the hypervisor 
(see arch/arm/arm*/entry.S). So the value you wrote in the register is 
overridden afterwards.
If you want to set the SS bit, you need to do in the save registered 
cpsr. You can access using:
guest_cpu_user_regs()->cpsr |= 0x200000;

Cheers,

--
Julien Grall

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