[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH 01/15] xen: x86: expose SGX to HVM domain in CPU featureset
On 09/07/17 09:04, Kai Huang wrote: > Expose SGX in CPU featureset for HVM domain. SGX will not be supported for > PV domain, as ENCLS (which SGX driver in guest essentially runs) must run > in ring 0, while PV kernel runs in ring 3. Theoretically we can support SGX > in PV domain via either emulating #GP caused by ENCLS running in ring 3, or > by PV ENCLS but it is really not necessary at this stage. And currently SGX > is only exposed to HAP HVM domain (we can add for shadow in the future). > > SGX Launch Control is also exposed in CPU featureset for HVM domain. SGX > Launch Control depends on SGX. > > Signed-off-by: Kai Huang <kai.huang@xxxxxxxxxxxxxxx> > --- > xen/include/public/arch-x86/cpufeatureset.h | 3 ++- > xen/tools/gen-cpuid.py | 3 +++ > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/xen/include/public/arch-x86/cpufeatureset.h > b/xen/include/public/arch-x86/cpufeatureset.h > index 97dd3534c5..b6c54e654e 100644 > --- a/xen/include/public/arch-x86/cpufeatureset.h > +++ b/xen/include/public/arch-x86/cpufeatureset.h > @@ -193,7 +193,7 @@ XEN_CPUFEATURE(XSAVES, 4*32+ 3) /*S > XSAVES/XRSTORS instructions */ > /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */ > XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /*A {RD,WR}{FS,GS}BASE instructions > */ > XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /*S TSC_ADJUST MSR available */ > -XEN_CPUFEATURE(SGX, 5*32+ 2) /* Software Guard extensions */ > +XEN_CPUFEATURE(SGX, 5*32+ 2) /*H Intel Software Guard extensions > */ > XEN_CPUFEATURE(BMI1, 5*32+ 3) /*A 1st bit manipulation extensions > */ > XEN_CPUFEATURE(HLE, 5*32+ 4) /*A Hardware Lock Elision */ > XEN_CPUFEATURE(AVX2, 5*32+ 5) /*A AVX2 instructions */ > @@ -229,6 +229,7 @@ XEN_CPUFEATURE(PKU, 6*32+ 3) /*H Protection > Keys for Userspace */ > XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */ > XEN_CPUFEATURE(AVX512_VPOPCNTDQ, 6*32+14) /*A POPCNT for vectors of DW/QW */ > XEN_CPUFEATURE(RDPID, 6*32+22) /*A RDPID instruction */ > +XEN_CPUFEATURE(SGX_LAUNCH_CONTROL, 6*32+30) /*H Intel SGX Launch Control */ Could we abbreviate this to SGX_LC ? It is certainly rather shorter to write, and appears to be used elsewhere. ~Andrew _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx https://lists.xen.org/xen-devel
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