Re: [Xen-devel] [PATCH v2 2/4] arm: smccc: handle SMCs/HVCs according to SMCCC

[Julien Grall <julien.grall@xxxxxxx>]

On 30/06/17 16:15, Julien Grall wrote:
> Now, looking at the documentation for ISS for SMC32 trap (D7-2271 and
> G6-4957 in ARM DDI 0487B.a), compare to other conditional instruction
> the ISS has an extra field CCKNOWNPASS (bit 19) to tell you whether CV
> and COND are valid.
>
> But on ARMv7, the ISS is UNK/SBZP. Meaning the software cannot rely on
> reading bits as all 0s. I have raised a question internally on how to
> write software compatible ARMv7 and ARMv8 AArch32. I will let you know
> the update.
>
> Meanwhile, I think you can prepare a patch to support CCKNOWNPASS for
> AArch32 and AArch64 (please mention the ARMv7 problem in it so we don't
> merge it until it is been figured out).
I got an answer on this one. The policy is Should-Be-Zero-Preserved, if 
you do read-modify-write you have to preserve the values. For read-only 
operation it will appear as 0 on older revision and 0/1 on new revision.
Cheers,

--
Julien Grall

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