[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH 4/6] xen/arm: platforms: Add Tegra platform to support basic IRQ routing
On Fri, Jul 7, 2017 at 2:53 PM, Chris Patterson <cjp256@xxxxxxxxx> wrote: > On Fri, Jul 7, 2017 at 12:30 PM, Julien Grall <julien.grall@xxxxxxx> wrote: >> Hi Chris, >> >> On 07/07/17 00:12, Chris Patterson wrote: >>>> >>>> >>>> So why do you want the hardware domain to interact with the ictlr? Could >>>> not >>>> you hide it completely? >>>> >>> >>> snip >>> >>>> What would happen if you enable the interrupt here for the guest? Should >>>> not >>>> you do it when the guest is requesting to enable (see vgic_enable_irqs). >>>> >>>> >>>> Also, how about EOI an interrupt? >>> >>> >>> We could possibly hide the legacy controller, but that has its own >>> challenges. Notably, the LIC allows configuration for forwarding FIQ >>> vs IRQ, and setting wake-up sources. >> >> >> FIQ are not supported for domain. So I am not sure why you would want a >> guest to configure that. >> > > Fair point, I did not know that and didn't want to assume there was > not a case otherwise... > >> Furthermore, could you explain what is wake-up sources and why a guest would >> need it? >> > > I would expect any driver using irq_set_irq_wake()? A little more > background from the reference manual > (http://developer.nvidia.com/embedded/dlc/tegra-x1-technical-reference-manual): > > " > The Legacy Interrupt Controller (LIC) is primarily used for BPMP > (ARM7). But it is also used for generating interrupts as wake > events for CPUs. This is an important use case when the core is in > retention. All of the device hardware interrupt signals are > sent to the LIC first, which routes them to the ARM7 BPMP-Lite as well > as forwards them to the GIC. The LIC also provides a > software set/clear mechanism for all of the interrupts." > > ... > > 3.3.1.5 Interrupt Blocking to Support Retention > > The Tegra X1 device implements blocking of interrupts routed to the > GIC, which supports the CPU retention state. The block > implementing this feature is represented in Figure 4 as Blocking. > > To support retention, the LIC contains a one shot disable for all the > interrupts. When the system goes into retention, BPMP > software sets this bit to disable the interrupts. > > The Flow Controller watches all the interrupts triggered and triggers > the BPMP to bring the core out of retention when any > interrupt bit is asserted. Once the system is out of retention, the > BLOCK _CCPLEX_GIC_INTR bit is cleared, and the interrupt is > serviced by the GIC. > " > > Anything using GPIO to wake (e.g. wifi?) is routed through the LIC. I > did not find anything obvious with a quick scan, but perhaps other > devices directly wired to the LIC may require it as well. > > Thoughts? Hey Julien. Just a quick ping. I was going to submit an updated patch series, just wanted to see if you had any further thoughts or desired changes with regards to the above. Thanks! _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx https://lists.xen.org/xen-devel
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