Re: [Xen-devel] [PATCH v6 05/16] x86: implement data structure and CPU init flow for MBA

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 08.10.17 at 09:23, <yi.y.sun@xxxxxxxxxxxxxxx> wrote:
> This patch implements main data structures of MBA.
> 
> Like CAT features, MBA HW info has cos_max which means the max thrtl
> register number, and thrtl_max which means the max throttle value
> (delay value). It also has a flag to represent if the throttle
> value is linear or non-linear.
> 
> One thrtl register of MBA stores a throttle value for one or more
> domains. The throttle value means the delay between L2 cache and next
> cache level.

It continues to be unclear to me what a delay between two
cache levels is. Perhaps "... the delay applied to traffic between
L2 cache and next cache level" (albeit the doc talks about core
and interconnect instead of cache levels).

> @@ -1442,13 +1527,13 @@ static void psr_cpu_init(void)
>          feat_l3 = NULL;
>  
>          if ( (regs.c & PSR_CAT_CDP_CAPABILITY) && (opt_psr & PSR_CDP) &&
> -             !cat_init_feature(&regs, feat, info, FEAT_TYPE_L3_CDP) )
> +             cat_init_feature(&regs, feat, info, FEAT_TYPE_L3_CDP) )
>              feat_props[FEAT_TYPE_L3_CDP] = &l3_cdp_props;
>  
>          /* If CDP init fails, try to work as L3 CAT. */
>          if ( !feat_props[FEAT_TYPE_L3_CDP] )
>          {
> -            if ( !cat_init_feature(&regs, feat, info, FEAT_TYPE_L3_CAT) )
> +            if ( cat_init_feature(&regs, feat, info, FEAT_TYPE_L3_CAT) )
>                  feat_props[FEAT_TYPE_L3_CAT] = &l3_cat_props;
>              else
>                  feat_l3 = feat;
> @@ -1461,12 +1546,24 @@ static void psr_cpu_init(void)
>  
>          feat = feat_l2_cat;
>          feat_l2_cat = NULL;
> -        if ( !cat_init_feature(&regs, feat, info, FEAT_TYPE_L2_CAT) )
> +        if ( cat_init_feature(&regs, feat, info, FEAT_TYPE_L2_CAT) )

All three changes above belong into patch 4 afaict.

Jan


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