[Xen-devel] [PATCH v6.5 15/26] x86/feature: Definitions for Indirect Branch Controls

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 04.01.18 at 01:15, <andrew.cooper3@xxxxxxxxxx> wrote:
> Contemporary processors are gaining Indirect Branch Controls via microcode
> updates.  Intel are introducing one bit to indicate IBRS and IBPB support, and
> a second bit for STIBP.  AMD are introducing IPBP only, so enumerate it with a
> separate bit.
> 
> Furthermore, depending on compiler and microcode availability, we may want to
> run Xen with IBRS set, or clear.
> 
> To use these facilities, we synthesise separate IBRS and IBPB bits for
> internal use.  A lot of infrastructure is required before these features are
> safe to offer to guests.
> 
> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>

As before
Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
despite my dislike of ...

> --- a/xen/include/asm-x86/msr-index.h
> +++ b/xen/include/asm-x86/msr-index.h
> @@ -31,6 +31,17 @@
>  #define EFER_LMSLE           (1<<_EFER_LMSLE)
>  #define EFER_FFXSE           (1<<_EFER_FFXSE)
>  
> +/* Speculation Controls. */
> +#define MSR_SPEC_CTRL                        0x00000048
> +#define _SPEC_CTRL_IBRS                      0
> +#define SPEC_CTRL_IBRS                       (_AC(1, ULL) << _SPEC_CTRL_IBRS)
> +#define _SPEC_CTRL_STIBP             1
> +#define SPEC_CTRL_STIBP                      (_AC(1, ULL) << 
> _SPEC_CTRL_STIBP)
> +
> +#define MSR_PRED_CMD                 0x00000049
> +#define _PRED_CMD_IBPB                       0
> +#define PRED_CMD_IBPB                        (_AC(1, ULL) << _PRED_CMD_IBPB)

... the further introduction of reserved names here (I do
realize this is consistent with other names in this file, but
anyway).

Jan


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