[Xen-devel] [PATCH RESEND v1 4/7] x86: add intel processor trace context

[Luwei Kang <luwei.kang@xxxxxxxxx>]

This patch add Intel processor trace context
date structure for guest.

Signed-off-by: Luwei Kang <luwei.kang@xxxxxxxxx>
---
 xen/include/asm-x86/hvm/vmx/vmcs.h |  3 +++
 xen/include/asm-x86/intel_pt.h     | 17 +++++++++++++++++
 xen/include/asm-x86/msr-index.h    | 20 ++++++++++++++++++++
 3 files changed, 40 insertions(+)

diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h 
b/xen/include/asm-x86/hvm/vmx/vmcs.h
index bd8a128..33ec3e6 100644
--- a/xen/include/asm-x86/hvm/vmx/vmcs.h
+++ b/xen/include/asm-x86/hvm/vmx/vmcs.h
@@ -20,6 +20,7 @@
 
 #include <asm/hvm/io.h>
 #include <irq_vectors.h>
+#include <asm/intel_pt.h>
 
 extern void vmcs_dump_vcpu(struct vcpu *v);
 extern void setup_vmcs_dump(void);
@@ -171,6 +172,8 @@ struct arch_vmx_struct {
      * pCPU and wakeup the related vCPU.
      */
     struct pi_blocking_vcpu pi_blocking;
+
+    struct pt_desc       pt_desc;
 };
 
 int vmx_create_vmcs(struct vcpu *v);
diff --git a/xen/include/asm-x86/intel_pt.h b/xen/include/asm-x86/intel_pt.h
index 2a8b579..909e22f 100644
--- a/xen/include/asm-x86/intel_pt.h
+++ b/xen/include/asm-x86/intel_pt.h
@@ -21,6 +21,23 @@
 #ifndef __ASM_X86_HVM_INTEL_PT_H_
 #define __ASM_X86_HVM_INTEL_PT_H_
 
+#include <asm/msr-index.h>
+
+struct pt_ctx {
+    u64 ctl;
+    u64 status;
+    u64 output_base;
+    u64 output_mask;
+    u64 cr3_match;
+    u64 addr[NUM_MSR_IA32_RTIT_ADDR];
+};
+
+struct pt_desc {
+    bool intel_pt_enabled;
+    unsigned int addr_num;
+    struct pt_ctx guest_pt_ctx;
+};
+
 extern bool_t opt_intel_pt;
 
 #endif /* __ASM_X86_HVM_INTEL_PT_H_ */
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index a834f3b..73c33be 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -529,4 +529,24 @@
 #define MSR_PKGC9_IRTL                 0x00000634
 #define MSR_PKGC10_IRTL                        0x00000635
 
+/* Intel PT MSRs */
+#define MSR_IA32_RTIT_CTL              0x00000570
+#define _MSR_IA32_RTIT_CTL_TRACEEN     0
+#define MSR_IA32_RTIT_CTL_TRACEEN      (1ULL << _MSR_IA32_RTIT_CTL_TRACEEN)
+#define _MSR_IA32_RTIT_CTL_TOPA                8
+#define MSR_IA32_RTIT_CTL_TOPA         (1ULL << _MSR_IA32_RTIT_CTL_TOPA)
+#define MSR_IA32_RTIT_STATUS           0x00000571
+#define MSR_IA32_RTIT_CR3_MATCH                0x00000572
+#define MSR_IA32_RTIT_OUTPUT_BASE      0x00000560
+#define MSR_IA32_RTIT_OUTPUT_MASK      0x00000561
+#define MSR_IA32_RTIT_ADDR0_A          0x00000580
+#define MSR_IA32_RTIT_ADDR0_B          0x00000581
+#define MSR_IA32_RTIT_ADDR1_A          0x00000582
+#define MSR_IA32_RTIT_ADDR1_B          0x00000583
+#define MSR_IA32_RTIT_ADDR2_A          0x00000584
+#define MSR_IA32_RTIT_ADDR2_B          0x00000585
+#define MSR_IA32_RTIT_ADDR3_A          0x00000586
+#define MSR_IA32_RTIT_ADDR3_B          0x00000587
+#define NUM_MSR_IA32_RTIT_ADDR         8
+
 #endif /* __ASM_MSR_INDEX_H */
-- 
1.8.3.1


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