[Xen-devel] [PATCH RESEND v1 6/7] x86: Implement Intel Processor Trace MSRs read/write

[Luwei Kang <luwei.kang@xxxxxxxxx>]

Intel PT MSRs read/write will not be intercepted when guest enabled
Intel PT. IA32_RTIT_CTL read/write will always cause a VM-Exit.

Signed-off-by: Luwei Kang <luwei.kang@xxxxxxxxx>
---
 xen/arch/x86/cpu/intel_pt.c    | 101 +++++++++++++++++++++++++++++++++++++++++
 xen/arch/x86/hvm/vmx/vmx.c     |  18 ++++++++
 xen/include/asm-x86/intel_pt.h |   4 ++
 3 files changed, 123 insertions(+)

diff --git a/xen/arch/x86/cpu/intel_pt.c b/xen/arch/x86/cpu/intel_pt.c
index c0e9e68..d530e57 100644
--- a/xen/arch/x86/cpu/intel_pt.c
+++ b/xen/arch/x86/cpu/intel_pt.c
@@ -28,6 +28,107 @@
 bool_t __read_mostly opt_intel_pt = 1;
 boolean_param("intel_pt", opt_intel_pt);
 
+
+static void intel_pt_disable_intercept_for_msr(u32 addr_num)
+{
+    struct vcpu *v = current;
+    int i;
+
+    vmx_clear_msr_intercept(v, MSR_IA32_RTIT_STATUS, VMX_MSR_RW);
+    vmx_clear_msr_intercept(v, MSR_IA32_RTIT_OUTPUT_BASE, VMX_MSR_RW);
+    vmx_clear_msr_intercept(v, MSR_IA32_RTIT_OUTPUT_MASK, VMX_MSR_RW);
+    vmx_clear_msr_intercept(v, MSR_IA32_RTIT_CR3_MATCH, VMX_MSR_RW);
+    for ( i = 0; i < addr_num; i++ )
+        vmx_clear_msr_intercept(v, MSR_IA32_RTIT_ADDR0_A + i, VMX_MSR_RW);
+}
+
+static void intel_pt_enable_intercept_for_msr(u32 addr_num)
+{
+    struct vcpu *v = current;
+    int i;
+
+    vmx_set_msr_intercept(v, MSR_IA32_RTIT_STATUS, VMX_MSR_RW);
+    vmx_set_msr_intercept(v, MSR_IA32_RTIT_OUTPUT_BASE, VMX_MSR_RW);
+    vmx_set_msr_intercept(v, MSR_IA32_RTIT_OUTPUT_MASK, VMX_MSR_RW);
+    vmx_set_msr_intercept(v, MSR_IA32_RTIT_CR3_MATCH, VMX_MSR_RW);
+    for ( i = 0; i < addr_num; i++ )
+        vmx_set_msr_intercept(v, MSR_IA32_RTIT_ADDR0_A + i, VMX_MSR_RW);
+}
+
+void pt_set_rtit_ctl(struct pt_desc *pt_desc, uint64_t msr_content)
+{
+    if (msr_content & MSR_IA32_RTIT_CTL_TRACEEN)
+        intel_pt_disable_intercept_for_msr(pt_desc->addr_num);
+    else
+        intel_pt_enable_intercept_for_msr(pt_desc->addr_num);
+
+    pt_desc->guest_pt_ctx.ctl = msr_content;
+
+    vmx_vmcs_enter(current);
+    __vmwrite(GUEST_IA32_RTIT_CTL, msr_content);
+    vmx_vmcs_exit(current);
+}
+
+int pt_do_rdmsr(unsigned int msr, uint64_t *msr_content)
+{
+    struct pt_desc *pt_desc = &current->arch.hvm_vmx.pt_desc;
+
+    if ( !opt_intel_pt )
+        return 1;
+
+    switch ( msr ) {
+    case MSR_IA32_RTIT_CTL:
+        *msr_content = pt_desc->guest_pt_ctx.ctl;
+        break;
+    case MSR_IA32_RTIT_STATUS:
+        *msr_content = pt_desc->guest_pt_ctx.status;
+        break;
+    case MSR_IA32_RTIT_OUTPUT_BASE:
+        *msr_content = pt_desc->guest_pt_ctx.output_base;
+        break;
+    case MSR_IA32_RTIT_OUTPUT_MASK:
+        *msr_content = pt_desc->guest_pt_ctx.output_mask;
+        break;
+    case MSR_IA32_RTIT_CR3_MATCH:
+        *msr_content = pt_desc->guest_pt_ctx.cr3_match;
+        break;
+    default:
+        *msr_content = pt_desc->guest_pt_ctx.addr[msr - MSR_IA32_RTIT_ADDR0_A];
+    }
+
+    return 0;
+}
+
+int pt_do_wrmsr(unsigned int msr, uint64_t msr_content)
+{
+    struct pt_desc *pt_desc = &current->arch.hvm_vmx.pt_desc;
+
+    if ( !opt_intel_pt )
+        return 1;
+
+    switch ( msr ) {
+    case MSR_IA32_RTIT_CTL:
+        pt_set_rtit_ctl(pt_desc, msr_content);
+        break;
+    case MSR_IA32_RTIT_STATUS:
+        pt_desc->guest_pt_ctx.status = msr_content;
+        break;
+    case MSR_IA32_RTIT_OUTPUT_BASE:
+        pt_desc->guest_pt_ctx.output_base = msr_content;
+        break;
+    case MSR_IA32_RTIT_OUTPUT_MASK:
+        pt_desc->guest_pt_ctx.output_mask = msr_content | 0x7F;
+        break;
+    case MSR_IA32_RTIT_CR3_MATCH:
+        pt_desc->guest_pt_ctx.cr3_match = msr_content;
+        break;
+    default:
+        pt_desc->guest_pt_ctx.addr[msr - MSR_IA32_RTIT_ADDR0_A] = msr_content;
+    }
+
+    return 0;
+}
+
 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_num)
 {
     u32 i;
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index f386933..e6713fd 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2929,6 +2929,15 @@ static int vmx_msr_read_intercept(unsigned int msr, 
uint64_t *msr_content)
         if ( vpmu_do_rdmsr(msr, msr_content) )
             goto gp_fault;
         break;
+    case MSR_IA32_RTIT_CTL:
+    case MSR_IA32_RTIT_STATUS:
+    case MSR_IA32_RTIT_OUTPUT_BASE:
+    case MSR_IA32_RTIT_OUTPUT_MASK:
+    case MSR_IA32_RTIT_CR3_MATCH:
+    case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
+        if ( pt_do_rdmsr(msr, msr_content) )
+            goto gp_fault;
+        break;
 
     default:
         if ( passive_domain_do_rdmsr(msr, msr_content) )
@@ -3149,6 +3158,15 @@ static int vmx_msr_write_intercept(unsigned int msr, 
uint64_t msr_content)
          if ( vpmu_do_wrmsr(msr, msr_content, 0) )
             goto gp_fault;
         break;
+    case MSR_IA32_RTIT_CTL:
+    case MSR_IA32_RTIT_STATUS:
+    case MSR_IA32_RTIT_OUTPUT_BASE:
+    case MSR_IA32_RTIT_OUTPUT_MASK:
+    case MSR_IA32_RTIT_CR3_MATCH:
+    case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
+        if ( pt_do_wrmsr(msr, msr_content) )
+            goto gp_fault;
+        break;
 
     default:
         if ( passive_domain_do_wrmsr(msr, msr_content) )
diff --git a/xen/include/asm-x86/intel_pt.h b/xen/include/asm-x86/intel_pt.h
index 9505c8f..5d51a12 100644
--- a/xen/include/asm-x86/intel_pt.h
+++ b/xen/include/asm-x86/intel_pt.h
@@ -40,6 +40,10 @@ struct pt_desc {
 
 extern bool_t opt_intel_pt;
 
+int pt_do_rdmsr(unsigned int msr, uint64_t *pdata);
+int pt_do_wrmsr(unsigned int msr, uint64_t data);
+void pt_set_rtit_ctl(struct pt_desc *pt_desc, uint64_t msr_content);
+
 void pt_vcpu_init(struct vcpu *v);
 void pt_guest_enter(struct vcpu *v);
 void pt_guest_exit(struct vcpu *v);
-- 
1.8.3.1


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