[Xen-devel] [PATCH 09/10] arm64: Add a handler for ICV_HPPIR1_EL1

[mjaggi@xxxxxxxxxxxxxxxxxx]

From: Manish Jaggi <manish.jaggi@xxxxxxxxxx>

Add a handler for reading the guest's view of the ICV_HPPIR1_EL1
register. This is a simple parsing of the available LRs, extracting the
highest available interrupt.

Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx>
---
 xen/arch/arm/arm64/vsysreg.c        | 24 ++++++++++++++++++++++++
 xen/include/asm-arm/arm64/sysregs.h |  1 +
 2 files changed, 25 insertions(+)

diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c
index 393d167e56..9bee678002 100644
--- a/xen/arch/arm/arm64/vsysreg.c
+++ b/xen/arch/arm/arm64/vsysreg.c
@@ -726,6 +726,26 @@ void handle_eoi(struct cpu_user_regs *regs, int regidx, 
const union hsr hsr)
     __vgic_v3_write_eoir(regs, regidx, hsr);
 }
 
+void handle_hppir1(struct cpu_user_regs *regs, int regidx, const union hsr hsr)
+{
+    u64 lr_val;
+    int lr, lr_grp, grp;
+    u32 vmcr = READ_SYSREG32(ICH_VMCR_EL2);
+
+    grp = __vgic_v3_get_group(hsr);
+    lr = __vgic_v3_highest_priority_lr(regs, vmcr, &lr_val);
+
+    if ( lr == -1 )
+        goto spurious;
+
+    lr_grp = !!(lr_val & ICH_LR_GROUP);
+    if ( lr_grp != grp )
+        lr_val = ICC_IAR1_EL1_SPURIOUS;
+
+spurious:
+    set_user_reg(regs, regidx, lr_val & ICH_LR_VIRTUAL_ID_MASK);
+}
+
 int do_fixup_vgic_errata(struct cpu_user_regs *regs, const union hsr hsr)
 {
     int ret = 0;
@@ -750,6 +770,10 @@ int do_fixup_vgic_errata(struct cpu_user_regs *regs, const 
union hsr hsr)
         handle_eoi(regs, regidx, hsr);
         break;
 
+    case HSR_SYSREG_ICC_HPPIR1_EL1:
+        handle_hppir1(regs, regidx, hsr);
+        break;
+
     default:
         ret = -1;
         break;
diff --git a/xen/include/asm-arm/arm64/sysregs.h 
b/xen/include/asm-arm/arm64/sysregs.h
index f9110ebf9c..c23c4a33b2 100644
--- a/xen/include/asm-arm/arm64/sysregs.h
+++ b/xen/include/asm-arm/arm64/sysregs.h
@@ -93,6 +93,7 @@
 #define HSR_SYSREG_ICC_IGRPEN1_EL1 HSR_SYSREG(3,0,c12,c12,7)
 #define HSR_SYSREG_ICC_IAR1_EL1   HSR_SYSREG(3,0,c12,c12,0)
 #define HSR_SYSREG_ICC_EOIR1_EL1  HSR_SYSREG(3,0,c12,c12,1)
+#define HSR_SYSREG_ICC_HPPIR1_EL1 HSR_SYSREG(3,0,c12,c12,2)
 #define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
 
 #define HSR_SYSREG_PMCR_EL0       HSR_SYSREG(3,3,c9,c12,0)
-- 
2.14.1


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