Re: [Xen-devel] [PATCH v8 08/17] x86/msr: Emulation of MSR_{SPEC_CTRL, PRED_CMD} for guests

[Andrew Cooper <Andrew.Cooper3@xxxxxxxxxx>]

________________________________________
From: Jan Beulich [JBeulich@xxxxxxxx]
Sent: 17 January 2018 09:11
To: Andrew Cooper
Cc: David Woodhouse; Xen-devel
Subject: Re: [Xen-devel] [PATCH v8 08/17] x86/msr: Emulation of MSR_{SPEC_CTRL, 
PRED_CMD} for guests

>>> On 16.01.18 at 17:58, <andrew.cooper3@xxxxxxxxxx> wrote:
> On 16/01/18 11:10, David Woodhouse wrote:
>> On Fri, 2018-01-12 at 18:00 +0000, Andrew Cooper wrote:
>>> @@ -152,14 +163,38 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr,
>>> uint64_t val)
>>>  {
>>>      const struct vcpu *curr = current;
>>>      struct domain *d = v->domain;
>>> +    const struct cpuid_policy *cp = d->arch.cpuid;
>>>      struct msr_domain_policy *dp = d->arch.msr;
>>>      struct msr_vcpu_policy *vp = v->arch.msr;
>>>
>>>      switch ( msr )
>>>      {
>>>      case MSR_INTEL_PLATFORM_INFO:
>>> +        /* Read-only */
>>>          goto gp_fault;
>>>
>>> +    case MSR_SPEC_CTRL:
>>> +        if ( !cp->feat.ibrsb )
>>> +            goto gp_fault; /* MSR available? */
>>> +        if ( val & ~(SPEC_CTRL_IBRS |
>>> +                     (cp->feat.stibp ? SPEC_CTRL_STIBP : 0)) )
>> Intel defines the STIBP bit as non-faulting and ignored, even when
>> STIBP isn't advertised. So you should probably just mask it out
>> if !cp->feat.stibp.
>
> Well - this published spec finally answers several several-month-old
> outstanding questions of mine.
>
> Time for some rewriting.  /sigh

In light of this, is there actually much point in me looking at the two
remaining v8 patches (13 and 14)?

Not really. They are going to change completely. 

~Andrew 

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