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Re: [Xen-devel] [RFC PATCH 34/49] ARM: new VGIC: Add CONFIG registers handlers
Hi Andre,
On 09/02/18 14:39, Andre Przywara wrote:
The config register handlers are shared between the v2 and v3 emulation,
so their implementation goes into vgic-mmio.c, to be easily referenced
from the v3 emulation as well later.
This is based on Linux commit 79717e4ac09c, written by Andre Przywara.
Signed-off-by: Andre Przywara <andre.przywara@xxxxxxxxxx>
---
xen/arch/arm/vgic/vgic-mmio-v2.c | 2 +-
xen/arch/arm/vgic/vgic-mmio.c | 54 ++++++++++++++++++++++++++++++++++++++++
xen/arch/arm/vgic/vgic-mmio.h | 7 ++++++
3 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c
index 0574ff9b16..c0b88b347e 100644
--- a/xen/arch/arm/vgic/vgic-mmio-v2.c
+++ b/xen/arch/arm/vgic/vgic-mmio-v2.c
@@ -98,7 +98,7 @@ static const struct vgic_register_region
vgic_v2_dist_registers[] = {
vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR,
- vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 2,
+ vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICD_SGIR,
vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c
index 14570d9d8e..626ce06986 100644
--- a/xen/arch/arm/vgic/vgic-mmio.c
+++ b/xen/arch/arm/vgic/vgic-mmio.c
@@ -356,6 +356,60 @@ void vgic_mmio_write_priority(struct vcpu *vcpu,
}
}
+unsigned long vgic_mmio_read_config(struct vcpu *vcpu,
+ paddr_t addr, unsigned int len)
Indentation.
+{
+ u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
uint32_t
+ u32 value = 0;
uint32_t.
+ int i;
unsigned int.
+
+ for ( i = 0; i < len * 4; i++ )
+ {
Same question as priority regarding the atomicity of ICFGR.
+ struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i);
+
+ if ( irq->config == VGIC_CONFIG_EDGE )
+ value |= (2U << (i * 2));
+
+ vgic_put_irq(vcpu->domain, irq);
+ }
+
+ return value;
+}
+
+void vgic_mmio_write_config(struct vcpu *vcpu,
+ paddr_t addr, unsigned int len,
+ unsigned long val)
Indentation
+{
+ u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
uint32_t
+ int i;
unsigned int
+ unsigned long flags;
+
+ for ( i = 0; i < len * 4; i++ )
+ {
+ struct vgic_irq *irq;
+
+ /*
+ * The configuration cannot be changed for SGIs in general,
+ * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
+ * code relies on PPIs being level triggered, so we also
+ * make them read-only here.
+ */
+ if ( intid + i < VGIC_NR_PRIVATE_IRQS )
+ continue;
+
+ irq = vgic_get_irq(vcpu->domain, vcpu, intid + i);
+ spin_lock_irqsave(&irq->irq_lock, flags);
+
+ if ( test_bit(i * 2 + 1, &val) )
+ irq->config = VGIC_CONFIG_EDGE;
+ else
+ irq->config = VGIC_CONFIG_LEVEL;
+
+ spin_unlock_irqrestore(&irq->irq_lock, flags);
+ vgic_put_irq(vcpu->domain, irq);
+ }
+}
+
static int match_region(const void *key, const void *elt)
{
const unsigned int offset = (unsigned long)key;
diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h
index 30221096b9..b42ea1bd8a 100644
--- a/xen/arch/arm/vgic/vgic-mmio.h
+++ b/xen/arch/arm/vgic/vgic-mmio.h
@@ -177,6 +177,13 @@ void vgic_mmio_write_priority(struct vcpu *vcpu,
paddr_t addr, unsigned int len,
unsigned long val);
+unsigned long vgic_mmio_read_config(struct vcpu *vcpu,
+ paddr_t addr, unsigned int len);
Indenation here and below.
+
+void vgic_mmio_write_config(struct vcpu *vcpu,
+ paddr_t addr, unsigned int len,
+ unsigned long val);
+
unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev);
/* Find the proper register handler entry given a certain address offset */
Cheers,
--
Julien Grall
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