[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 2/5] x86/pv: Avoid leaking other guests' MSR_TSC_AUX values into PV context
If the CPU pipeline supports RDTSCP or RDPID, a guest can observe the value in MSR_TSC_AUX, irrespective of whether the relevant CPUID features are advertised/hidden. At the moment, paravirt_ctxt_switch_to() only writes to MSR_TSC_AUX if TSC_MODE_PVRDTSCP mode is enabled, but this is not the default mode. Therefore, default PV guests can read the value from a previously scheduled HVM vcpu, or TSC_MODE_PVRDTSCP-enabled PV guest. Alter the PV path to always write to MSR_TSC_AUX, using 0 in the common case. To amortise overhead cost, introduce wrmsr_tsc_aux() which performs a lazy update of the MSR, and use this function consistently across the codebase. Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> --- CC: Jan Beulich <JBeulich@xxxxxxxx> CC: Jun Nakajima <jun.nakajima@xxxxxxxxx> CC: Kevin Tian <kevin.tian@xxxxxxxxx> CC: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> CC: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx> CC: Wei Liu <wei.liu2@xxxxxxxxxx> CC: Roger Pau Monné <roger.pau@xxxxxxxxxx> CC: Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx> N.B. This has been deemed not a security issue, because the MSR doesn't store any sensitive information. --- xen/arch/x86/domain.c | 6 +++--- xen/arch/x86/hvm/hvm.c | 2 +- xen/arch/x86/hvm/svm/svm.c | 2 +- xen/arch/x86/hvm/vmx/vmx.c | 2 +- xen/arch/x86/msr.c | 2 ++ xen/include/asm-x86/msr.h | 16 ++++++++++++++-- 6 files changed, 22 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index f93327b..9c3527f 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1533,9 +1533,9 @@ void paravirt_ctxt_switch_to(struct vcpu *v) if ( unlikely(v->arch.debugreg[7] & DR7_ACTIVE_MASK) ) activate_debugregs(v); - if ( (v->domain->arch.tsc_mode == TSC_MODE_PVRDTSCP) && - boot_cpu_has(X86_FEATURE_RDTSCP) ) - write_rdtscp_aux(v->domain->arch.incarnation); + if ( cpu_has_rdtscp ) + wrmsr_tsc_aux(v->domain->arch.tsc_mode == TSC_MODE_PVRDTSCP + ? v->domain->arch.incarnation : 0); } /* Update per-VCPU guest runstate shared memory area (if registered). */ diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 5d39210..0539551 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -3579,7 +3579,7 @@ int hvm_msr_write_intercept(unsigned int msr, uint64_t msr_content, v->arch.hvm_vcpu.msr_tsc_aux = (uint32_t)msr_content; if ( cpu_has_rdtscp && (v->domain->arch.tsc_mode != TSC_MODE_PVRDTSCP) ) - wrmsrl(MSR_TSC_AUX, (uint32_t)msr_content); + wrmsr_tsc_aux(msr_content); break; case MSR_IA32_APICBASE: diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 9f58afc..f53f430 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1093,7 +1093,7 @@ static void svm_ctxt_switch_to(struct vcpu *v) svm_tsc_ratio_load(v); if ( cpu_has_rdtscp ) - wrmsrl(MSR_TSC_AUX, hvm_msr_tsc_aux(v)); + wrmsr_tsc_aux(hvm_msr_tsc_aux(v)); } static void noreturn svm_do_resume(struct vcpu *v) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 5cd689e..31acb0e 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -618,7 +618,7 @@ static void vmx_restore_guest_msrs(struct vcpu *v) } if ( cpu_has_rdtscp ) - wrmsrl(MSR_TSC_AUX, hvm_msr_tsc_aux(v)); + wrmsr_tsc_aux(hvm_msr_tsc_aux(v)); } void vmx_update_cpu_exec_control(struct vcpu *v) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 7875d9c..7ba9a10 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -24,6 +24,8 @@ #include <xen/sched.h> #include <asm/msr.h> +DEFINE_PER_CPU(uint32_t, tsc_aux); + struct msr_domain_policy __read_mostly hvm_max_msr_domain_policy, __read_mostly pv_max_msr_domain_policy; diff --git a/xen/include/asm-x86/msr.h b/xen/include/asm-x86/msr.h index 928f1cc..9475a71 100644 --- a/xen/include/asm-x86/msr.h +++ b/xen/include/asm-x86/msr.h @@ -115,8 +115,6 @@ static inline uint64_t rdtsc_ordered(void) __write_tsc(val); \ }) -#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) - #define rdpmc(counter,low,high) \ __asm__ __volatile__("rdpmc" \ : "=a" (low), "=d" (high) \ @@ -210,6 +208,20 @@ static inline void write_efer(uint64_t val) DECLARE_PER_CPU(u32, ler_msr); +DECLARE_PER_CPU(uint32_t, tsc_aux); + +/* Lazy update of MSR_TSC_AUX */ +static inline void wrmsr_tsc_aux(uint32_t val) +{ + uint32_t *this_tsc_aux = &this_cpu(tsc_aux); + + if ( *this_tsc_aux != val ) + { + wrmsr(MSR_TSC_AUX, val, 0); + *this_tsc_aux = val; + } +} + /* MSR policy object for shared per-domain MSRs */ struct msr_domain_policy { -- 2.1.4 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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