Re: [Xen-devel] [PATCH RFC 3/3] xtf: add minimal HPET functionality test

[Roger Pau Monné <roger.pau@xxxxxxxxxx>]

On Thu, Mar 01, 2018 at 03:04:29AM -0700, Jan Beulich wrote:
> >>> On 01.03.18 at 10:55, <roger.pau@xxxxxxxxxx> wrote:
> > On Wed, Feb 28, 2018 at 09:24:09AM -0700, Jan Beulich wrote:
> >> >>> On 28.02.18 at 16:37, <roger.pau@xxxxxxxxxx> wrote:
> >> > On Fri, Feb 23, 2018 at 07:07:18PM +0000, Wei Liu wrote:
> >> >> On Fri, Feb 23, 2018 at 01:27:43PM +0000, Roger Pau Monne wrote:
> >> >> > --- a/arch/x86/include/arch/lib.h
> >> >> > +++ b/arch/x86/include/arch/lib.h
> >> >> > @@ -392,6 +392,20 @@ static inline void write_xcr0(uint64_t xcr0)
> >> >> >      xsetbv(0, xcr0);
> >> >> >  }
> >> >> >  
> >> >> > +static inline uint64_t rdtsc(void)
> >> >> > +{
> >> >> > +    uint32_t low, high;
> >> >> > +
> >> >> > +    asm volatile ("rdtsc" : "=a" (low), "=d" (high));
> >> >> > +
> >> >> 
> >> >> You probably need to add lfence or mfence. See rdtsc_ordered in Xen.
> >> > 
> >> > Oh, OK that's news to me. I guess just using a lfence before it
> >> > should be fine.
> >> 
> >> Except that on AMD, without LFENCE made dispatch serializing,
> >> you'd need MFENCE.
> > 
> > So using just MFENCE will work everywhere since that's more
> > restrictive than a lfence?
> 
> Sadly no. I think that's explained in the description of the
> hypervisor patches introducing rdtsc_ordered(), but you can also
> simply read up on the LFENCE/MFENCE specifics on the Intel SDM
> instruction description. In particular: "MFENCE does not serialize
> the instruction stream." Yet that's what we're after here. MFENCE
> is a serializing instruction on AMD hardware only.

Hm, nice. Then I basically need to issue both a LFENCE and MFENCE
because I don't plan to introduce an alternatives framework to XTF
ATM.

Thanks, Roger.

_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxxx
https://lists.xenproject.org/mailman/listinfo/xen-devel