[Xen-devel] [PATCH v3 0/6] unsafe big.LITTLE support

[Stefano Stabellini <sstabellini@xxxxxxxxxx>]

Hi all,

This series changes the initialization of two virtual registers to make
sure they match the value of the underlying physical cpu.

It also disables cpus different from the boot cpu, unless a newly
introduced command line option is specified. In that case, it explains
how to setup the system to avoid corruptions, which involves manually
specifying the cpu affinity of all domains, because the scheduler still
lacks big.LITTLE support.

In the uncommon case of a system where the cacheline sizes are different
across cores, it disables all cores that have a different cacheline size
from the boot cpu. In fact, it is not sufficient to use the cacheline
size of the current cpu, it would be necessary to use the minimum across
all cacheline sizes of all cores.  Given that it is actually uncommon
even in big.LITTLE systems, just disable cpus for now.

Cheers,

Stefano


Julien Grall (1):
      xen/arm: Park CPUs with a MIDR different from the boot CPU.

Stefano Stabellini (5):
      xen/arm: make processor a per cpu variable
      xen/arm: read ACTLR on the pcpu where the vcpu will run
      xen/arm: set VPIDR based on the MIDR value of the underlying pCPU
      xen/arm: update the docs about heterogeneous computing
      xen/arm: disable CPUs with different cacheline sizes

 docs/misc/arm/big.LITTLE.txt        | 46 +++++++++++++++++++++++++++++++++++++
 docs/misc/xen-command-line.markdown | 15 ++++++++++++
 xen/arch/arm/domain.c               | 15 ++++++------
 xen/arch/arm/processor.c            |  8 +++----
 xen/arch/arm/setup.c                | 15 +-----------
 xen/arch/arm/smpboot.c              | 39 +++++++++++++++++++++++++++++++
 xen/arch/arm/vcpreg.c               |  4 ++--
 xen/include/asm-arm/domain.h        |  3 ---
 xen/include/asm-arm/page.h          | 12 ++++++++++
 9 files changed, 126 insertions(+), 31 deletions(-)
 create mode 100644 docs/misc/arm/big.LITTLE.txt

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