Re: [Xen-devel] [PATCH 00/12] arm64: Mediate access to GICv3 sysregs at EL2

[Julien Grall <julien.grall@xxxxxxx>]

Hi,

Manish, I don't monitor my linaro email and would appreciate if you use 
the e-mail address provided by MAINTAINERS.
Cheers,


On 12/03/18 12:42, mjaggi@xxxxxxxxxxxxxxxxxx wrote:
> From: Manish Jaggi <manish.jaggi@xxxxxxxxxx>
>
> This patchset is a Xen port of Marc's patchset.
> arm64: KVM: Mediate access to GICv3 sysregs at EL2 [1]
>
> The current RFC patchset is a subset of [1], as it handleing only Group1 traps
> as a PoC. Most of the trap code is added in vsysreg.c. Trap handler function is 
> kept
> independent of the usual guest trap handling code.
> Looking for feedback on this approach.
>
> The errata has been validated on Cavium ThunderX platform.
>
> Steps to reporduce the errata
> - Boot Xen with 2 cores.
> - Disable group1 interrupts in domU kernel
> - start domU, the kill and start again.
> One of the Xen core would hang.
>
> Code in this patchset fixes this issue.
>
> [1] https://lists.cs.columbia.edu/pipermail/kvmarm/2017-June/026029.html
>
> Changes from RFC
> - Added commit information on ported patches from linux
> - Added skip_hyp_tail to control calling leave_hypervisor_tail
> - Added CAVIUM_CONFIG_ERRATUM_30115 which will auto enable workaround
>
> Manish Jaggi (12):
>    arm:Kconfig Rename menu text
>    arm64: cputype: Add MIDR values for Cavium ThunderX1 CPUs
>    arm64: Add config for Cavium Thunder erratum 30115
>    Enable Group1 Traps by default for Cavium ThunderX
>    Placeholder for handling Group1 register traps
>    arm64: vgic-v3: Add ICV_BPR1_EL1 handler
>    arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler
>    arm64: Add accessors for the ICH_APxRn_EL2 registers
>    Expose ich_read/write_lr in vsysreg_errata.c
>    arm64: Add ICV_IAR1_EL1 handler
>    arm64: vgic-v3: Add ICV_EOIR1_EL1 handler
>    arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler
>
>   xen/arch/arm/Kconfig                |   6 +-
>   xen/arch/arm/arm64/Makefile         |   1 +
>   xen/arch/arm/arm64/vsysreg_errata.c | 660 ++++++++++++++++++++++++++++++++++++
>   xen/arch/arm/cpuerrata.c            |  21 ++
>   xen/arch/arm/gic-v3.c               |  16 +-
>   xen/arch/arm/traps.c                |  20 ++
>   xen/include/asm-arm/arm64/sysregs.h |   5 +
>   xen/include/asm-arm/arm64/traps.h   |   3 +-
>   xen/include/asm-arm/cpuerrata.h     |   1 +
>   xen/include/asm-arm/cpufeature.h    |   3 +-
>   xen/include/asm-arm/current.h       |   1 +
>   xen/include/asm-arm/gic.h           |   1 +
>   xen/include/asm-arm/gic_v3_defs.h   |  29 ++
>   xen/include/asm-arm/processor.h     |   9 +
>   14 files changed, 771 insertions(+), 5 deletions(-)
>   create mode 100644 xen/arch/arm/arm64/vsysreg_errata.c
--
Julien Grall

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