Re: [Xen-devel] [PATCH v4 2/8] x86: disable XPTI when RDCL_NO

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 19.03.18 at 14:38, <JBeulich@xxxxxxxx> wrote:
> Use the respective ARCH_CAPABILITIES MSR bit, but don't expose the MSR
> to guests yet.
> 
> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
> Tested-by: Juergen Gross <jgross@xxxxxxxx>
> Reviewed-by: Juergen Gross <jgross@xxxxxxxx>
> Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> ---
> v3: Re-base.
> v2: New.

And I realize I've once again forgot to Cc the two of you for the
smallish tools side changes.

Jan

> --- a/tools/libxl/libxl_cpuid.c
> +++ b/tools/libxl/libxl_cpuid.c
> @@ -204,6 +204,7 @@ int libxl_cpuid_parse_config(libxl_cpuid
>          {"avx512-4fmaps",0x00000007,  0, CPUID_REG_EDX,  3,  1},
>          {"ibrsb",        0x00000007,  0, CPUID_REG_EDX, 26,  1},
>          {"stibp",        0x00000007,  0, CPUID_REG_EDX, 27,  1},
> +        {"arch-caps",    0x00000007,  0, CPUID_REG_EDX, 29,  1},
>  
>          {"lahfsahf",     0x80000001, NA, CPUID_REG_ECX,  0,  1},
>          {"cmplegacy",    0x80000001, NA, CPUID_REG_ECX,  1,  1},
> --- a/tools/misc/xen-cpuid.c
> +++ b/tools/misc/xen-cpuid.c
> @@ -143,6 +143,7 @@ static const char *str_7d0[32] =
>      [ 2] = "avx512_4vnniw", [ 3] = "avx512_4fmaps",
>  
>      [26] = "ibrsb",         [27] = "stibp",
> +    /* 28 */                [29] = "arch_caps",
>  };
>  
>  static struct {
> --- a/xen/arch/x86/setup.c
> +++ b/xen/arch/x86/setup.c
> @@ -1547,7 +1547,16 @@ void __init noreturn __start_xen(unsigne
>      cr4_pv32_mask = mmu_cr4_features & XEN_CR4_PV32_BITS;
>  
>      if ( opt_xpti < 0 )
> -        opt_xpti = boot_cpu_data.x86_vendor != X86_VENDOR_AMD;
> +    {
> +        uint64_t caps = 0;
> +
> +        if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
> +            caps = ARCH_CAPABILITIES_RDCL_NO;
> +        else if ( boot_cpu_has(X86_FEATURE_ARCH_CAPS) )
> +            rdmsrl(MSR_ARCH_CAPABILITIES, caps);
> +
> +        opt_xpti = !(caps & ARCH_CAPABILITIES_RDCL_NO);
> +    }
>      if ( opt_xpti )
>          setup_clear_cpu_cap(X86_FEATURE_NO_XPTI);
>      else
> --- a/xen/include/asm-x86/msr-index.h
> +++ b/xen/include/asm-x86/msr-index.h
> @@ -40,6 +40,8 @@
>  #define PRED_CMD_IBPB                        (_AC(1, ULL) << 0)
>  
>  #define MSR_ARCH_CAPABILITIES                0x0000010a
> +#define ARCH_CAPABILITIES_RDCL_NO    (_AC(1, ULL) << 0)
> +#define ARCH_CAPABILITIES_IBRS_ALL   (_AC(1, ULL) << 1)
>  
>  /* Intel MSRs. Some also available on other CPUs */
>  #define MSR_IA32_PERFCTR0            0x000000c1
> --- a/xen/include/public/arch-x86/cpufeatureset.h
> +++ b/xen/include/public/arch-x86/cpufeatureset.h
> @@ -244,6 +244,7 @@ XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /
>  XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A  AVX512 Multiply Accumulation 
> Single Precision */
>  XEN_CPUFEATURE(IBRSB,         9*32+26) /*A  IBRS and IBPB support (used by 
> Intel) */
>  XEN_CPUFEATURE(STIBP,         9*32+27) /*A! STIBP */
> +XEN_CPUFEATURE(ARCH_CAPS,     9*32+29) /*   IA32_ARCH_CAPABILITIES MSR */
>  
>  #endif /* XEN_CPUFEATURE */
>  
> 
> 
> 
> 
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@xxxxxxxxxxxxxxxxxxxx 
> https://lists.xenproject.org/mailman/listinfo/xen-devel 




_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxxx
https://lists.xenproject.org/mailman/listinfo/xen-devel