[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v4 2/7] x86/xpti: don't flush TLB twice when switching to 64-bit pv context
When switching to a 64-bit pv context the TLB is flushed twice today: the first time when switching to the new address space in write_ptbase(), the second time when switching to guest mode in restore_to_guest. Avoid the first TLB flush in that case. Signed-off-by: Juergen Gross <jgross@xxxxxxxx> --- V3: - omit setting root_pgt_changed to false (Jan Beulich) --- xen/arch/x86/mm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index b1d3f0eda8..f7d24a1f8b 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -123,6 +123,7 @@ #include <asm/io_apic.h> #include <asm/pci.h> #include <asm/guest.h> +#include <asm/processor.h> #include <asm/hvm/grant_table.h> #include <asm/pv/grant_table.h> @@ -503,9 +504,13 @@ void make_cr3(struct vcpu *v, mfn_t mfn) void write_ptbase(struct vcpu *v) { - if ( this_cpu(root_pgt) ) + if ( this_cpu(root_pgt) && is_pv_vcpu(v) && !is_pv_32bit_vcpu(v) ) + { get_cpu_info()->root_pgt_changed = true; - write_cr3(v->arch.cr3); + asm volatile ( "mov %0, %%cr3" : : "r" (v->arch.cr3) : "memory" ); + } + else + write_cr3(v->arch.cr3); } /* -- 2.13.6 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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