[Xen-devel] [PATCH v2 01/17] arm: Placeholder for handling Group0/1 traps

[Manish Jaggi <manish.jaggi@xxxxxxxxxx>]

The errata will require to emulate the GIC virtual CPU interface in Xen. 
Because the hypervisor will update its internal state of the vGIC, we want
to avoid messing up with it. So the errata is handled separately from the
rest of the hypervisor.

New file vgic-v3-sr.c is added which will hold trap and emulate code
for group0 / group1 registers. Workaround for cavium Errata 30115
needs this emulation code.

vgic_v3_handle_cpuif_access would be called from do_trap_guest_sync
in subsequent patches based on errata macros.

Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx>
---
 xen/arch/arm/arm64/vgic-v3-sr.c   | 60 +++++++++++++++++++++++++++++++++++++++
 xen/include/asm-arm/arm64/traps.h |  2 ++
 2 files changed, 62 insertions(+)
 create mode 100644 xen/arch/arm/arm64/vgic-v3-sr.c

diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
new file mode 100644
index 0000000000..39ab1ed6ca
--- /dev/null
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -0,0 +1,60 @@
+/*
+ * xen/arch/arm/arm64/vgic-v3-sr.c
+ *
+ * Code to emulate group0/group1 traps for handling
+ * cavium erratum 30115
+ *
+ * Manish Jaggi <manish.jaggi@xxxxxxxxxx>
+ * Copyright (c) 2018 Cavium.
+ *
+ * Ths program is free software; you can redistribute it and/or
+ * modify it under the terms and conditions of the GNU General Public
+ * License, version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/current.h>
+#include <asm/regs.h>
+#include <asm/system.h>
+#include <asm/traps.h>
+
+/*
+ * returns true if the register is emulated.
+ */
+bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs)
+{
+    bool ret = true;
+    const union hsr hsr = { .bits = regs->hsr };
+
+    /* Disabling interrupts to prevent change in guest state */
+    local_irq_disable();
+    if ( hsr.ec != HSR_EC_SYSREG )
+    {
+        ret = false;
+        goto end;
+    }
+
+    switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
+    {
+    default:
+        ret = false;
+        break;
+    }
+end:
+    local_irq_enable();
+
+    return ret;
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/arm64/traps.h 
b/xen/include/asm-arm/arm64/traps.h
index 2379b578cb..3c3911a69c 100644
--- a/xen/include/asm-arm/arm64/traps.h
+++ b/xen/include/asm-arm/arm64/traps.h
@@ -3,6 +3,8 @@
 
 void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len);
 
+bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs);
+
 void do_sysreg(struct cpu_user_regs *regs,
                const union hsr hsr);
 
-- 
2.14.1


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