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Re: [Xen-devel] [PATCH 2/3] x86: suppress BTI mitigations around S3 suspend/resume



On 13/04/18 19:25, Simon Gaiser wrote:
> Jan Beulich:
>> NMI and #MC can occur at any time after S3 resume, yet the MSR_SPEC_CTRL
>> may become available only once we're reloaded microcode. Make
>> SPEC_CTRL_ENTRY_FROM_INTR_IST and DO_SPEC_CTRL_EXIT_TO_XEN no-ops for
>> the critical period of time.
>>
>> Also set the MSR back to its intended value.
>>
>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
>>
>> --- a/xen/arch/x86/acpi/power.c
>> +++ b/xen/arch/x86/acpi/power.c
>> @@ -28,6 +28,7 @@
>>  #include <asm/tboot.h>
>>  #include <asm/apic.h>
>>  #include <asm/io_apic.h>
>> +#include <asm/spec_ctrl.h>
>>  #include <acpi/cpufreq/cpufreq.h>
>>  
>>  uint32_t system_reset_counter = 1;
>> @@ -163,6 +164,7 @@ static int enter_state(u32 state)
>>  {
>>      unsigned long flags;
>>      int error;
>> +    struct cpu_info *ci;
>>      unsigned long cr4;
>>  
>>      if ( (state <= ACPI_STATE_S0) || (state > ACPI_S_STATES_MAX) )
>> @@ -210,6 +212,10 @@ static int enter_state(u32 state)
>>      else
>>          error = 0;
>>  
>> +    ci = get_cpu_info();
>> +    ci->use_shadow_spec_ctrl = 0;
>> +    ci->bti_ist_info = 0;
>> +
>>      ACPI_FLUSH_CPU_CACHE();
>>  
>>      switch ( state )
>> @@ -248,6 +254,11 @@ static int enter_state(u32 state)
>>  
>>      microcode_resume_cpu(0);
>>  
>> +    ci->bti_ist_info = default_bti_ist_info;
>> +    asm volatile (ALTERNATIVE("", "wrmsr", X86_FEATURE_XEN_IBRS_SET)
> This does not compile for me:
>
>   power.c: Assembler messages:
>   power.c:272: Error: value of 257 too large for field of 1 bytes at 0
>
> Changing the alternative based on the other "wrmsr" calls fixes it:
>
>   asm volatile (ALTERNATIVE(ASM_NOP3, "wrmsr", X86_FEATURE_XEN_IBRS_SET)

Ah - you're presumably back-porting this to 4.8?

Jan's code is correct for staging, and your version here is correct for
all currently-released versions of Xen.  (I've done quite a lot of
playing with alternatives generation for 4.11.)

~Andrew

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