Re: [Xen-devel] [PATCH RESEND v1 5/7] x86: Implement Intel Processor Trace context switch

[Wei Liu <wei.liu2@xxxxxxxxxx>]

On Fri, Apr 27, 2018 at 08:53:30AM +0000, Kang, Luwei wrote:
> > > Load/Store Intel processor trace register in context switch.
> > > MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS.
> > > When Intel PT is supported in guest, we need load/restore PT MSRs only
> > > when PT is enabled in guest.
> > >
> > > Signed-off-by: Luwei Kang <luwei.kang@xxxxxxxxx>
> > 
> > Is there a reason to not use xsaves/xrstors when they are available?
> > 
> There have two method to implement context switch(manual and xsave/xrstors).
> The first method is more directly and also won't have any performance 
> overhead if intel PT is disabled.
> If use xsave/xrstors we need to check if it available and whether PT is 
> supported  in XSS (CPUID.0D(ecx=1).ecx).
> I will think about this scenario and may make an independent patch to enable 
> it. 

Fair enough.

I figure Xen doesn't understand xsaves (among other xsave* features) at
the moment so a dedicated series to enable that is required.

Wei.

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