Re: [Xen-devel] [PATCH RESEND v1 6/7] x86: Implement Intel Processor Trace MSRs read/write

["Kang, Luwei" <luwei.kang@xxxxxxxxx>]

> >      Thanks for your clarification. Please correct me if I have
> > something wrong. Guest may execute an instruction and this instruction
> > may produce an PT packet save in PT output buffer. An EPT violation
> > will be generated if the address of this PT buffer don't have EPT page
> > table mapping, but this EPT violations shouldn't be handled by
> > x86_emulate() because it no relate with the execute of this instruction.
> 
> Plus - and that's very important - the EPT violation may be reported on some 
> later insn.

Hi Jan,
You mean the "later instruction" is some new instruction in future hardware?  
Is there have something need we attention or any different with current 
instruction which can lead EPT violation? Sorry, I didn't catch your concern. 

> 
> >      In that case, can we build the EPT map when set the output buffer
> > address (IA32_RTIT_OUTPUT_BASE) and crash the guest if still happened
> > EPT violation with Intel PT output buffer read/write exit
> > qualification. Or add an exit qualification check before instruction 
> > emulation?
> 
> Imo you should add an exit qualification check in any case. Depending what 
> else you do, finding the new bit set may imply crashing
> the domain or doing something more sophisticated.

Do you mean add this check at the beginning of any specific "exit_reason" 
handler in vmx_vmexit_handler() function?
Another question is where to build this EPT mapping? Setting 
IA32_RTIT_OUTPUT_BASE or handled by EPT violation?

Thanks,
Luwei Kang

> 
> Jan
> 


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