[Xen-devel] [PATCH v3 01/17] arm: Placeholder code to handle guest GICv3 sysreg accesses at EL2

[Manish Jaggi <mjaggi@xxxxxxxxxxxxxxxxxx>]

From: Manish Jaggi <manish.jaggi@xxxxxxxxxx>

The errata will require emulation of GIC virtual CPU interface in Xen.
Because the hypervisor will update its internal state of the vGIC, we
want to avoid messing up with it. So the errata is handled separately
from the rest of the hypervisor.

New file vgic-v3-sr.c is added which will hold trap and emulate code
for group0 / group1 registers.

vgic_v3_handle_cpuif_access would be called from do_trap_guest_sync
(xen/arch/arm/traps.c) in subsequent patches based on
check_errata_workaround macro.

This patch takes some code from linux commit:
59da1cbfd840d69bd7a310249924da3fc202c417
(KVM: arm64: vgic-v3: Add hook to handle guest GICv3 sysreg accesses at
EL2)

vgic_v3_read/write_vmcr functions are imported from linux commit:
commit 328e566479449194979d64685ae6d74c989599bb
(KVM: arm/arm64: vgic: Defer touching GICH_VMCR to vcpu_load/put)
Since only two small functions are imported and is a dependency to match
imported linux code single patch is used.

Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx>

diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
new file mode 100644
index 0000000000..4cc077fbb6
--- /dev/null
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -0,0 +1,86 @@
+/*
+ * xen/arch/arm/arm64/vgic-v3-sr.c
+ *
+ * Code to emulate group0/group1 traps for handling
+ * cavium erratum 30115
+ *
+ * This file merges code from Linux virt/kvm/arm/hyp/vgic-v3-sr.c
+ * which is : Copyright (C) 2012-2015 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@xxxxxxx>
+ *
+ * Xen-Merge: Manish Jaggi <manish.jaggi@xxxxxxxxxx>
+ *
+ * Ths program is free software; you can redistribute it and/or
+ * modify it under the terms and conditions of the GNU General Public
+ * License, version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/current.h>
+#include <asm/regs.h>
+#include <asm/system.h>
+#include <asm/traps.h>
+
+/* Provide wrappers to read write VMCR similar to linux */
+static uint64_t vgic_v3_read_vmcr(void)
+{
+    return READ_SYSREG32(ICH_VMCR_EL2);
+}
+
+static void vgic_v3_write_vmcr(uint32_t vmcr)
+{
+    WRITE_SYSREG32(vmcr, ICH_VMCR_EL2);
+}
+
+/* vgic_v3_handle_cpuif_access
+ * returns: true if the register is emulated
+ *          false if not a sysreg
+ */
+bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs)
+{
+    int rt;
+    uint32_t vmcr;
+    void (*fn)(struct cpu_user_regs *, u32, int);
+    bool is_read;
+    uint32_t sysreg;
+    bool ret = true;
+    const union hsr hsr = { .bits = regs->hsr };
+
+    sysreg = hsr.bits & HSR_SYSREG_REGS_MASK;
+    is_read = hsr.sysreg.read;
+    /* Disabling interrupts to prevent change in guest state */
+    local_irq_disable();
+    if ( hsr.ec != HSR_EC_SYSREG )
+    {
+        ret = false;
+        goto end;
+    }
+
+    switch ( sysreg )
+    {
+    default:
+        ret = false;
+        goto end;
+    }
+    /* Call the emulation hander */
+    vmcr = vgic_v3_read_vmcr();
+    rt = hsr.sysreg.reg;
+    fn(regs, vmcr, rt);
+end:
+    local_irq_enable();
+
+    return ret;
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/arm64/traps.h 
b/xen/include/asm-arm/arm64/traps.h
index 2379b578cb..3c3911a69c 100644
--- a/xen/include/asm-arm/arm64/traps.h
+++ b/xen/include/asm-arm/arm64/traps.h
@@ -3,6 +3,8 @@
 
 void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len);
 
+bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs);
+
 void do_sysreg(struct cpu_user_regs *regs,
                const union hsr hsr);
 
-- 
2.14.1


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