[Xen-devel] [PATCH v3 08/17] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler

[Manish Jaggi <mjaggi@xxxxxxxxxxxxxxxxxx>]

This patch is ported from linux to xen
commit: 2724c11a1df4b22ee966c04809ea0e808f66b04e
(KVM: arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler)

Add a handler for reading the guest's view of the ICV_HPPIR1_EL1
register. This is a simple parsing of the available LRs, extracting the
highest available interrupt.

Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx>

diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 2192547cc4..c067278499 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -593,6 +593,27 @@ static void vgic_v3_write_eoir(struct cpu_user_regs *regs, 
uint32_t vmcr,
     vgic_v3_clear_active_lr(lr, lr_val);
 }
 
+static void vgic_v3_read_hppir(struct cpu_user_regs *regs, uint32_t vmcr,
+                               int rt)
+{
+    uint64_t lr_val;
+    int lr, lr_grp, grp;
+    const union hsr hsr = { .bits = regs->hsr };
+
+    grp = vgic_v3_get_group(hsr);
+    lr = vgic_v3_highest_priority_lr(regs, vmcr, &lr_val);
+
+    if ( lr == -1 )
+        goto spurious;
+
+    lr_grp = !!(lr_val & ICH_LR_GROUP);
+    if ( lr_grp != grp )
+        lr_val = ICC_IAR1_EL1_SPURIOUS;
+
+spurious:
+    set_user_reg(regs, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
+}
+
 /* vgic_v3_handle_cpuif_access
  * returns: true if the register is emulated
  *          false if not a sysreg
@@ -642,6 +663,10 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs 
*regs)
         fn = vgic_v3_write_eoir;
         break;
 
+    case HSR_SYSREG_ICC_HPPIR1_EL1:
+        fn = vgic_v3_read_hppir;
+        break;
+
     default:
         ret = false;
         goto end;
diff --git a/xen/include/asm-arm/arm64/sysregs.h 
b/xen/include/asm-arm/arm64/sysregs.h
index f7422f1649..b9230fe795 100644
--- a/xen/include/asm-arm/arm64/sysregs.h
+++ b/xen/include/asm-arm/arm64/sysregs.h
@@ -93,6 +93,7 @@
 #define HSR_SYSREG_ICC_IGRPEN1_EL1 HSR_SYSREG(3,0,c12,c12,7)
 #define HSR_SYSREG_ICC_IAR1_EL1   HSR_SYSREG(3,0,c12,c12,0)
 #define HSR_SYSREG_ICC_EOIR1_EL1  HSR_SYSREG(3,0,c12,c12,1)
+#define HSR_SYSREG_ICC_HPPIR1_EL1 HSR_SYSREG(3,0,c12,c12,2)
 #define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
 
 #define HSR_SYSREG_PMCR_EL0       HSR_SYSREG(3,3,c9,c12,0)
-- 
2.14.1


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