Re: [Xen-devel] [RFC PATCH 07/12] hvmloader: allocate MMCONFIG area in the MMIO hole + minor code refactoring

[Alexey G <x1917x@xxxxxxxxx>]

>On Wed, 30 May 2018 03:56:07 +1000
>Alexey G <x1917x@xxxxxxxxx> wrote:
>
>>On Tue, 29 May 2018 08:23:51 -0600
>>"Jan Beulich" <JBeulich@xxxxxxxx> wrote:
>>  
>>>>>> On 12.03.18 at 19:33, <x1917x@xxxxxxxxx> wrote:      
>>>> --- a/tools/firmware/hvmloader/config.h
>>>> +++ b/tools/firmware/hvmloader/config.h
>>>> @@ -53,10 +53,14 @@ extern uint8_t ioapic_version;
>>>>  #define PCI_ISA_DEVFN       0x08    /* dev 1, fn 0 */
>>>>  #define PCI_ISA_IRQ_MASK    0x0c20U /* ISA IRQs 5,10,11 are PCI connected 
>>>> */
>>>>  #define PCI_ICH9_LPC_DEVFN  0xf8    /* dev 31, fn 0 */
>>>> +#define PCI_MCH_DEVFN       0       /* bus 0, dev 0, func 0 */      
>>>
>>>Just MCH is liable to become ambiguous in the future. Perhaps 
>>>PCI_Q35_MCH_DEVFN?    
>>
>>Agree, PCI_Q35_MCH_DEVFN is more explicit.

On the other thought, we can reuse one MCH BDF #define for multiple
emulated chipsets, not just for something completely distinct to Q35
but even for those which mostly require merely changing PCI DIDs (like
P35 etc.) So in this case producing multiple #defines like
PCI_{Q|P|G}35_MCH_DEVFN for the same BDF 0:0.0 might be excessive.

PCI_ICH9_LPC_DEVFN can be actually reused too, its BDF location
survived many chipset generations so its #define can be shared as well
(though renamed to something like PCI_LPC_BRIDGE_DEVFN).

>>>> @@ -172,10 +173,14 @@ void pci_setup(void)
>>>>  
>>>>      /* Create a list of device BARs in descending order of size. */
>>>>      struct bars {
>>>> -        uint32_t is_64bar;
>>>>          uint32_t devfn;
>>>>          uint32_t bar_reg;
>>>>          uint64_t bar_sz;
>>>> +        uint64_t addr_mask; /* which bits of the base address can be 
>>>> written */
>>>> +        uint32_t bar_data;  /* initial value - BAR flags here */      
>>>

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