Re: [Xen-devel] [PATCH v2 07/10] x86: Add Intel Processor Trace MSRs read/write emulation

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 03.07.18 at 12:18, <luwei.kang@xxxxxxxxx> wrote:
>> > --- a/xen/arch/x86/hvm/vmx/vmx.c
>> > +++ b/xen/arch/x86/hvm/vmx/vmx.c
>> > @@ -2898,6 +2898,15 @@ static int vmx_msr_read_intercept(unsigned int
>> > msr, uint64_t *msr_content)
>> >          if ( vpmu_do_rdmsr(msr, msr_content) )
>> >              goto gp_fault;
>> >          break;
>> > +    case MSR_IA32_RTIT_CTL:
>> > +    case MSR_IA32_RTIT_STATUS:
>> > +    case MSR_IA32_RTIT_OUTPUT_BASE:
>> > +    case MSR_IA32_RTIT_OUTPUT_MASK:
>> > +    case MSR_IA32_RTIT_CR3_MATCH:
>> > +    case MSR_IA32_RTIT_ADDR_A(0) ... MSR_IA32_RTIT_ADDR_B(3):
>> 
>> Is the 3 here an architectural limit? Otherwise you want to use a higher 
> number here and rely on the callee to do the full checking.
>> 
> 
> "3" is the max number of address ranges which I can find in spec. The number 
> of address ranges is get from CPUID info. Will fix it.

Question is what the largest number is that the designated CPUID output
field can hold.

Jan



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