Re: [Xen-devel] [PATCH 5/6] x86/HVM: prefill cache with PDPTEs when possible

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 19.07.18 at 13:15, <andrew.cooper3@xxxxxxxxxx> wrote:
> On 19/07/18 11:50, Jan Beulich wrote:
>> Since strictly speaking it is incorrect for guest_walk_tables() to read
>> L3 entries during PAE page walks, try to overcome this where possible by
>> pre-loading the values from hardware into the cache. Sadly the
>> information is available in the EPT case only. On the positive side for
>> NPT the spec spells out that L3 entries are actually read on walks, so
>> us reading them is consistent with hardware behavior in that case.
>>
>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
> 
> I'm afraid that this isn't architecturally correct.  It means that an
> emulated memory access will read the PDPTE register values, rather than
> what is actually in RAM.

I'm afraid I don't understand: A CR3 load loads the PDPTEs into
registers, and walks use those registers, not memory. That's the very
difference between PAE and all other walks.

Jan



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