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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v3 3/6] xen/arm: zynqmp: introduce zynqmp specific defines
From: "Edgar E. Iglesias" <edgar.iglesias@xxxxxxxxxx> From: Edgar E. Iglesias <edgar.iglesias@xxxxxxxxxx> Introduce zynqmp specific defines for the firmware calls. See EEMI: https://www.xilinx.com/support/documentation/user_guides/ug1200-eemi-api.pdf The error codes are described, under XIlPM Error Codes: https://www.xilinx.com/support/documentation/user_guides/ug1137-zynq-ultrascale-mpsoc-swdev.pdf Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xxxxxxxxxx> Signed-off-by: Stefano Stabellini <stefanos@xxxxxxxxxx> --- xen/include/asm-arm/platforms/xilinx-zynqmp-eemi.h | 383 +++++++++++++++++++++ 1 file changed, 383 insertions(+) diff --git a/xen/include/asm-arm/platforms/xilinx-zynqmp-eemi.h b/xen/include/asm-arm/platforms/xilinx-zynqmp-eemi.h index 6630dc8..70fad7a 100644 --- a/xen/include/asm-arm/platforms/xilinx-zynqmp-eemi.h +++ b/xen/include/asm-arm/platforms/xilinx-zynqmp-eemi.h @@ -1,3 +1,386 @@ #include <asm/processor.h> +#define MM_CRL_APB 0xff5e0000 +#define MM_RPU 0xff9a0000 +#define MM_RTC 0xffa60000 +#define MM_ADMA_CH0 0xffa80000 + +#define MM_USB3_0_XHCI 0xfe200000 +#define MM_USB3_1_XHCI 0xfe300000 + +#define MM_SATA_AHCI_HBA 0xfd0c0000 +#define MM_AXIPCIE_MAIN 0xfd0e0000 +#define MM_CRF_APB 0xfd1a0000 +#define MM_PCIE_ATTRIB 0xfd480000 +#define MM_DP 0xfd4a0000 +#define MM_GPU 0xfd4b0000 +#define MM_GDMA_CH0 0xfd500000 + +#define MM_UART0 0xff000000 +#define MM_UART1 0xff010000 +#define MM_I2C0 0xff020000 +#define MM_I2C1 0xff030000 +#define MM_SPI0 0xff040000 +#define MM_SPI1 0xff050000 +#define MM_CAN0 0xff060000 +#define MM_CAN1 0xff070000 +#define MM_GPIO 0xff0a0000 +#define MM_GEM0 0xff0b0000 +#define MM_GEM1 0xff0c0000 +#define MM_GEM2 0xff0d0000 +#define MM_GEM3 0xff0e0000 +#define MM_QSPI 0xff0f0000 +#define MM_NAND 0xff100000 +#define MM_TTC0 0xff110000 +#define MM_TTC1 0xff120000 +#define MM_TTC2 0xff130000 +#define MM_TTC3 0xff140000 +#define MM_SWDT 0xff150000 +#define MM_SD0 0xff160000 +#define MM_SD1 0xff170000 +#define MM_IOU_SLCR 0xff180000 + +#define MM_PMU_GLOBAL 0xffd80000 + +/* Selected set of register definitions: */ +#define R_CRF_APLL_CTRL 0x20 +#define R_CRF_ACPU_CTRL 0x60 +#define R_CRF_DP_VIDEO_REF_CTRL 0x70 +#define R_CRF_DP_AUDIO_REF_CTRL 0x74 +#define R_CRF_DP_STC_REF_CTRL 0x7c +#define R_CRF_GPU_REF_CTRL 0x84 +#define R_CRF_SATA_REF_CTRL 0xa0 +#define R_CRF_PCIE_REF_CTRL 0xb4 +#define R_CRF_GDMA_REF_CTRL 0xb8 +#define R_CRF_DPDMA_REF_CTRL 0xbc + +#define R_CRL_IOPLL_CTRL 0x20 +#define R_CRL_RPLL_TO_FPD_CTRL 0x48 +#define R_CRL_USB3_DUAL_REF_CTRL 0x4c +#define R_CRL_GEM0_REF_CTRL 0x50 +#define R_CRL_GEM1_REF_CTRL 0x54 +#define R_CRL_GEM2_REF_CTRL 0x58 +#define R_CRL_GEM3_REF_CTRL 0x5c +#define R_CRL_USB0_BUS_REF_CTRL 0x60 +#define R_CRL_USB1_BUS_REF_CTRL 0x64 +#define R_CRL_QSPI_REF_CTRL 0x68 +#define R_CRL_SDIO0_REF_CTRL 0x6c +#define R_CRL_SDIO1_REF_CTRL 0x70 +#define R_CRL_UART0_REF_CTRL 0x74 +#define R_CRL_UART1_REF_CTRL 0x78 +#define R_CRL_SPI0_REF_CTRL 0x7c +#define R_CRL_SPI1_REF_CTRL 0x80 +#define R_CRL_CAN0_REF_CTRL 0x84 +#define R_CRL_CAN1_REF_CTRL 0x88 +#define R_CRL_CPU_R5_CTRL 0x90 +#define R_CRL_IOU_SWITCH_CTRL 0x9c +#define R_CRL_CSU_PLL_CTRL 0xa0 +#define R_CRL_PCAP_CTRL 0xa4 +#define R_CRL_LPD_SWITCH_CTRL 0xa8 +#define R_CRL_LPD_LSBUS_CTRL 0xac +#define R_CRL_DBG_LPD_CTRL 0xb0 +#define R_CRL_NAND_REF_CTRL 0xb4 +#define R_CRL_ADMA_REF_CTRL 0xb8 +#define R_CRL_PL0_REF_CTRL 0xc0 +#define R_CRL_PL1_REF_CTRL 0xc4 +#define R_CRL_PL2_REF_CTRL 0xc8 +#define R_CRL_PL3_REF_CTRL 0xcc +#define R_CRL_PL0_THR_CTRL 0xd0 +#define R_CRL_PL0_THR_CNT 0xd4 +#define R_CRL_PL1_THR_CTRL 0xd8 +#define R_CRL_PL1_THR_CNT 0xdc +#define R_CRL_PL2_THR_CTRL 0xe0 +#define R_CRL_PL2_THR_CNT 0xe4 +#define R_CRL_PL3_THR_CTRL 0xe8 +#define R_CRL_PL3_THR_CNT 0xfc +#define R_CRL_GEM_TSU_REF_CTRL 0x100 +#define R_CRL_DLL_REF_CTRL 0x104 +#define R_CRL_AMS_REF_CTRL 0x108 +#define R_CRL_I2C0_REF_CTRL 0x120 +#define R_CRL_I2C1_REF_CTRL 0x124 +#define R_CRL_TIMESTAMP_REF_CTRL 0x128 + +#define R_PMU_GLOBAL_GLOBAL_GEN_STORAGE0 0x30 +#define R_PMU_GLOBAL_PERS_GLOB_GEN_STORAGE7 0x6c + +#define R_PMU_GLOBAL_PWR_STATE 0x100 + +#define R_IOU_SLCR_MIO_PIN_0 0x0 +#define R_IOU_SLCR_MIO_MST_TRI2 0x20c +#define R_IOU_SLCR_WDT_CLK_SEL 0x300 +#define R_IOU_SLCR_CAN_MIO_CTRL 0x304 +#define R_IOU_SLCR_GEM_CLK_CTRL 0x308 +#define R_IOU_SLCR_SDIO_CLK_CTRL 0x30c +#define R_IOU_SLCR_CTRL_REG_SD 0x310 +#define R_IOU_SLCR_SD_ITAPDLY 0x314 +#define R_IOU_SLCR_SD_CDN_CTRL 0x35c +#define R_IOU_SLCR_GEM_CTRL 0x360 +#define R_IOU_SLCR_IOU_TTC_APB_CLK 0x380 +#define R_IOU_SLCR_IOU_TAPDLY_BYPASS 0x390 +#define R_IOU_SLCR_IOU_COHERENT_CTRL 0x400 +#define R_IOU_SLCR_VIDEO_PSS_CLK_SEL 0x404 +#define R_IOU_SLCR_IOU_RAM_GEM0 0x500 +#define R_IOU_SLCR_IOU_RAM_GEM1 0x504 +#define R_IOU_SLCR_IOU_RAM_GEM2 0x508 +#define R_IOU_SLCR_IOU_RAM_GEM3 0x50c +#define R_IOU_SLCR_IOU_RAM_SD0 0x510 +#define R_IOU_SLCR_IOU_RAM_SD1 0x514 +#define R_IOU_SLCR_IOU_RAM_CAN0 0x518 +#define R_IOU_SLCR_IOU_RAM_CAN1 0x51c +#define R_IOU_SLCR_IOU_RAM_LQSPI 0x520 +#define R_IOU_SLCR_IOU_RAM_NAND 0x524 + +/* Service calls. */ +#define PM_GET_TRUSTZONE_VERSION 0xa03 + +/* SMC function IDs for SiP Service queries */ +#define ZYNQMP_SIP_SVC_CALL_COUNT 0xff00 +#define ZYNQMP_SIP_SVC_UID 0xff01 +#define ZYNQMP_SIP_SVC_VERSION 0xff03 + +enum pm_api_id { + /* Miscellaneous API functions: */ + PM_GET_API_VERSION = 1, /* Do not change or move */ + PM_SET_CONFIGURATION, + PM_GET_NODE_STATUS, + PM_GET_OP_CHARACTERISTIC, + PM_REGISTER_NOTIFIER, + /* API for suspending of PUs: */ + PM_REQ_SUSPEND, + PM_SELF_SUSPEND, + PM_FORCE_POWERDOWN, + PM_ABORT_SUSPEND, + PM_REQ_WAKEUP, + PM_SET_WAKEUP_SOURCE, + PM_SYSTEM_SHUTDOWN, + /* API for managing PM slaves: */ + PM_REQ_NODE, + PM_RELEASE_NODE, + PM_SET_REQUIREMENT, + PM_SET_MAX_LATENCY, + /* Direct control API functions: */ + PM_RESET_ASSERT, + PM_RESET_GET_STATUS, + PM_MMIO_WRITE, + PM_MMIO_READ, + PM_INIT, + PM_FPGA_LOAD, + PM_FPGA_GET_STATUS, + PM_GET_CHIPID, + /* ID 25 is been used by U-boot to process secure boot images */ + /* Secure library generic API functions */ + PM_SECURE_SHA = 26, + PM_SECURE_RSA, + /* Pin control API functions */ + PM_PINCTRL_REQUEST, + PM_PINCTRL_RELEASE, + PM_PINCTRL_GET_FUNCTION, + PM_PINCTRL_SET_FUNCTION, + PM_PINCTRL_CONFIG_PARAM_GET, + PM_PINCTRL_CONFIG_PARAM_SET, + /* PM IOCTL API */ + PM_IOCTL, + /* API to query information from firmware */ + PM_QUERY_DATA, + /* Clock control API functions */ + PM_CLOCK_ENABLE, + PM_CLOCK_DISABLE, + PM_CLOCK_GETSTATE, + PM_CLOCK_SETDIVIDER, + PM_CLOCK_GETDIVIDER, + PM_CLOCK_SETRATE, + PM_CLOCK_GETRATE, + PM_CLOCK_SETPARENT, + PM_CLOCK_GETPARENT, + PM_API_MAX +}; + +enum pm_node_id { + NODE_RPU = 6, + NODE_RPU_0, + NODE_RPU_1, + NODE_GPU_PP_0 = 20, + NODE_GPU_PP_1, + NODE_USB_0, + NODE_USB_1, + NODE_TTC_0, + NODE_TTC_1, + NODE_TTC_2, + NODE_TTC_3, + NODE_SATA, + NODE_ETH_0, + NODE_ETH_1, + NODE_ETH_2, + NODE_ETH_3, + NODE_UART_0, + NODE_UART_1, + NODE_SPI_0, + NODE_SPI_1, + NODE_I2C_0, + NODE_I2C_1, + NODE_SD_0, + NODE_SD_1, + NODE_DP, + NODE_GDMA, + NODE_ADMA, + NODE_NAND, + NODE_QSPI, + NODE_GPIO, + NODE_CAN_0, + NODE_CAN_1, + NODE_AFI, + NODE_APLL, + NODE_VPLL, + NODE_DPLL, + NODE_RPLL, + NODE_IOPLL, + NODE_DDR, + NODE_IPI_APU, + NODE_IPI_RPU_0, + NODE_GPU, + NODE_PCIE, + NODE_PCAP, + NODE_RTC, +}; + +/** + * @XST_PM_SUCCESS: Success + * @XST_PM_INTERNAL: Unexpected error + * @XST_PM_CONFLICT: Conflicting requirements + * @XST_PM_NO_ACCESS: Access rights violation + * @XST_PM_INVALID_NODE: Does not apply to node passed as argument + * @XST_PM_DOUBLE_REQ: Duplicate request + * @XST_PM_ABORT_SUSPEND: Target has aborted suspend + */ +enum pm_ret_status { + XST_PM_SUCCESS = 0, + XST_PM_INTERNAL = 2000, + XST_PM_CONFLICT, + XST_PM_NO_ACCESS, + XST_PM_INVALID_NODE, + XST_PM_DOUBLE_REQ, + XST_PM_ABORT_SUSPEND, +}; + +enum pm_reset { + XILPM_RESET_START = 999, + XILPM_RESET_PCIE_CFG, + XILPM_RESET_PCIE_BRIDGE, + XILPM_RESET_PCIE_CTRL, + XILPM_RESET_DP, + XILPM_RESET_SWDT_CRF, + XILPM_RESET_AFI_FM5, + XILPM_RESET_AFI_FM4, + XILPM_RESET_AFI_FM3, + XILPM_RESET_AFI_FM2, + XILPM_RESET_AFI_FM1, + XILPM_RESET_AFI_FM0, + XILPM_RESET_GDMA, + XILPM_RESET_GPU_PP1, + XILPM_RESET_GPU_PP0, + XILPM_RESET_GPU, + XILPM_RESET_GT, + XILPM_RESET_SATA, + XILPM_RESET_ACPU3_PWRON, + XILPM_RESET_ACPU2_PWRON, + XILPM_RESET_ACPU1_PWRON, + XILPM_RESET_ACPU0_PWRON, + XILPM_RESET_APU_L2, + XILPM_RESET_ACPU3, + XILPM_RESET_ACPU2, + XILPM_RESET_ACPU1, + XILPM_RESET_ACPU0, + XILPM_RESET_DDR, + XILPM_RESET_APM_FPD, + XILPM_RESET_SOFT, + XILPM_RESET_GEM0, + XILPM_RESET_GEM1, + XILPM_RESET_GEM2, + XILPM_RESET_GEM3, + XILPM_RESET_QSPI, + XILPM_RESET_UART0, + XILPM_RESET_UART1, + XILPM_RESET_SPI0, + XILPM_RESET_SPI1, + XILPM_RESET_SDIO0, + XILPM_RESET_SDIO1, + XILPM_RESET_CAN0, + XILPM_RESET_CAN1, + XILPM_RESET_I2C0, + XILPM_RESET_I2C1, + XILPM_RESET_TTC0, + XILPM_RESET_TTC1, + XILPM_RESET_TTC2, + XILPM_RESET_TTC3, + XILPM_RESET_SWDT_CRL, + XILPM_RESET_NAND, + XILPM_RESET_ADMA, + XILPM_RESET_GPIO, + XILPM_RESET_IOU_CC, + XILPM_RESET_TIMESTAMP, + XILPM_RESET_RPU_R50, + XILPM_RESET_RPU_R51, + XILPM_RESET_RPU_AMBA, + XILPM_RESET_OCM, + XILPM_RESET_RPU_PGE, + XILPM_RESET_USB0_CORERESET, + XILPM_RESET_USB1_CORERESET, + XILPM_RESET_USB0_HIBERRESET, + XILPM_RESET_USB1_HIBERRESET, + XILPM_RESET_USB0_APB, + XILPM_RESET_USB1_APB, + XILPM_RESET_IPI, + XILPM_RESET_APM_LPD, + XILPM_RESET_RTC, + XILPM_RESET_SYSMON, + XILPM_RESET_AFI_FM6, + XILPM_RESET_LPD_SWDT, + XILPM_RESET_FPD, + XILPM_RESET_RPU_DBG1, + XILPM_RESET_RPU_DBG0, + XILPM_RESET_DBG_LPD, + XILPM_RESET_DBG_FPD, + XILPM_RESET_APLL, + XILPM_RESET_DPLL, + XILPM_RESET_VPLL, + XILPM_RESET_IOPLL, + XILPM_RESET_RPLL, + XILPM_RESET_GPO3_PL_0, + XILPM_RESET_GPO3_PL_1, + XILPM_RESET_GPO3_PL_2, + XILPM_RESET_GPO3_PL_3, + XILPM_RESET_GPO3_PL_4, + XILPM_RESET_GPO3_PL_5, + XILPM_RESET_GPO3_PL_6, + XILPM_RESET_GPO3_PL_7, + XILPM_RESET_GPO3_PL_8, + XILPM_RESET_GPO3_PL_9, + XILPM_RESET_GPO3_PL_10, + XILPM_RESET_GPO3_PL_11, + XILPM_RESET_GPO3_PL_12, + XILPM_RESET_GPO3_PL_13, + XILPM_RESET_GPO3_PL_14, + XILPM_RESET_GPO3_PL_15, + XILPM_RESET_GPO3_PL_16, + XILPM_RESET_GPO3_PL_17, + XILPM_RESET_GPO3_PL_18, + XILPM_RESET_GPO3_PL_19, + XILPM_RESET_GPO3_PL_20, + XILPM_RESET_GPO3_PL_21, + XILPM_RESET_GPO3_PL_22, + XILPM_RESET_GPO3_PL_23, + XILPM_RESET_GPO3_PL_24, + XILPM_RESET_GPO3_PL_25, + XILPM_RESET_GPO3_PL_26, + XILPM_RESET_GPO3_PL_27, + XILPM_RESET_GPO3_PL_28, + XILPM_RESET_GPO3_PL_29, + XILPM_RESET_GPO3_PL_30, + XILPM_RESET_GPO3_PL_31, + XILPM_RESET_RPU_LS, + XILPM_RESET_PS_ONLY, + XILPM_RESET_PL, + XILPM_RESET_END +}; + extern bool zynqmp_eemi(struct cpu_user_regs *regs); -- 1.9.1 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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