[Xen-devel] [PATCH for-4.6] amend "x86/Intel: Mitigations for GPZ SP4 - Speculative Store Bypass"

["Jan Beulich" <JBeulich@xxxxxxxx>]

This is part of CVE-2018-3639 / XSA-263.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/tools/libxc/xc_cpufeature.h
+++ b/tools/libxc/xc_cpufeature.h
@@ -147,5 +147,6 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (edx) */
 #define X86_FEATURE_IBRSB       26 /* IBRS and IBPB support (used by Intel) */
 #define X86_FEATURE_STIBP       27 /* STIBP */
+#define X86_FEATURE_SSBD        31 /* MSR_SPEC_CTRL.SSBD available */
 
 #endif /* __LIBXC_CPUFEATURE_H */
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -369,7 +369,8 @@ static void xc_cpuid_hvm_policy(
                         bitmaskof(X86_FEATURE_SMAP) |
                         bitmaskof(X86_FEATURE_FSGSBASE));
             regs[3] &= (bitmaskof(X86_FEATURE_IBRSB) |
-                        bitmaskof(X86_FEATURE_STIBP));
+                        bitmaskof(X86_FEATURE_STIBP) |
+                        bitmaskof(X86_FEATURE_SSBD));
         } else
             regs[1] = regs[3] = 0;
         regs[0] = regs[2] = 0;
@@ -512,7 +513,8 @@ static void xc_cpuid_pv_policy(
                         bitmaskof(X86_FEATURE_ADX)  |
                         bitmaskof(X86_FEATURE_FSGSBASE));
             regs[3] &= (bitmaskof(X86_FEATURE_IBRSB) |
-                        bitmaskof(X86_FEATURE_STIBP));
+                        bitmaskof(X86_FEATURE_STIBP) |
+                        bitmaskof(X86_FEATURE_SSBD));
         }
         else
             regs[1] = regs[3] = 0;





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