Re: [Xen-devel] [PATCH v2 3/4] x86/HVM: implement memory read caching

[Wei Liu <wei.liu2@xxxxxxxxxx>]

On Tue, Sep 11, 2018 at 07:15:19AM -0600, Jan Beulich wrote:
> Emulation requiring device model assistance uses a form of instruction
> re-execution, assuming that the second (and any further) pass takes
> exactly the same path. This is a valid assumption as far use of CPU
> registers goes (as those can't change without any other instruction
> executing in between), but is wrong for memory accesses. In particular
> it has been observed that Windows might page out buffers underneath an
> instruction currently under emulation (hitting between two passes). If
> the first pass translated a linear address successfully, any subsequent
> pass needs to do so too, yielding the exact same translation.

Not sure I follow. If the buffers are paged out between two passes, how
would caching the translation help?  Yes you get the same translation
result but the content of the address pointed to by the translation
result could be different, right?

Wei.

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