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Re: [Xen-devel] [PATCH v2] x86/HVM: correct hvmemul_map_linear_addr() for multi-page case
- To: Jan Beulich <JBeulich@xxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Tue, 25 Sep 2018 16:30:07 +0100
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- Cc: xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Paul Durrant <paul.durrant@xxxxxxxxxx>
- Delivery-date: Tue, 25 Sep 2018 16:18:35 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Openpgp: preference=signencrypt
On 25/09/18 13:41, Jan Beulich wrote:
>>>> On 20.09.18 at 14:41, <andrew.cooper3@xxxxxxxxxx> wrote:
>> On 13/09/18 11:12, Jan Beulich wrote:
>>> The function does two translations in one go for a single guest access.
>>> Any failure of the first translation step (guest linear -> guest
>>> physical), resulting in #PF, ought to take precedence over any failure
>>> of the second step (guest physical -> host physical).
>> Why? What is the basis of this presumption?
>>
>> As far as what real hardware does...
>>
>> This test sets up a ballooned page and a read-only page. I.e. a second
>> stage fault on the first part of a misaligned access, and a first stage
>> fault on the second part of the access.
>>
>> (d1) --- Xen Test Framework ---
>> (d1) Environment: HVM 64bit (Long mode 4 levels)
>> (d1) Test splitfault
>> (d1) About to read
>> (XEN) *** EPT qual 0000000000000181, gpa 000000000011cffc
>> (d1) Reading PTR: got 00000000ffffffff
>> (d1) About to write
>> (XEN) *** EPT qual 0000000000000182, gpa 000000000011cffc
>> (d1) ******************************
>> (d1) PANIC: Unhandled exception at 0008:00000000001047e0
>> (d1) Vec 14 #PF[-d-sWP] %cr2 000000000011d000
>> (d1) ******************************
>>
>> The second stage fault is recognised first, which is contrary to your
>> presumption, i.e. the code in its current form appears to be correct.
> Coming back to this example of yours: As a first step, are we in
> agreement that with the exception of very complex instructions
> (FSAVE, FXSAVE, XSAVE etc) instructions are supposed to work in an
> all-or-nothing manner when it comes to updating of architectural
> state (be it registers or memory)?
No. Read Chapter Intel Vol3 8.1 and 8.2, which makes it quite clear
that misaligned accesses may be split access, and observably so to other
processors in the system.
I've even found a new bit in it which says that >quadword SSE accesses
may even result in a partial write being completed before #PF is raised.
~Andrew
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