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Re: [Xen-devel] Ping: [PATCH v3 0/4] x86/HVM: implement memory read caching
- To: Jan Beulich <JBeulich@xxxxxxxx>, George Dunlap <George.Dunlap@xxxxxxxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Tue, 2 Oct 2018 11:51:37 +0100
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- Cc: xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Paul Durrant <paul.durrant@xxxxxxxxxx>
- Delivery-date: Tue, 02 Oct 2018 10:51:51 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Openpgp: preference=signencrypt
On 02/10/18 11:36, Jan Beulich wrote:
>>>> On 25.09.18 at 16:14, <JBeulich@xxxxxxxx> wrote:
>> Emulation requiring device model assistance uses a form of instruction
>> re-execution, assuming that the second (and any further) pass takes
>> exactly the same path. This is a valid assumption as far as use of CPU
>> registers goes (as those can't change without any other instruction
>> executing in between), but is wrong for memory accesses. In particular
>> it has been observed that Windows might page out buffers underneath
>> an instruction currently under emulation (hitting between two passes).
>> If the first pass translated a linear address successfully, any subsequent
>> pass needs to do so too, yielding the exact same translation.
>>
>> Introduce a cache (used just by guest page table accesses for now, i.e.
>> a form of "paging structure cache") to make sure above described
>> assumption holds. This is a very simplistic implementation for now: Only
>> exact matches are satisfied (no overlaps or partial reads or anything).
>>
>> There's also some seemingly unrelated cleanup here which was found
>> desirable on the way.
>>
>> 1: x86/mm: add optional cache to GLA->GFN translation
>> 2: x86/mm: use optional cache in guest_walk_tables()
>> 3: x86/HVM: implement memory read caching
>> 4: x86/HVM: prefill cache with PDPTEs when possible
>>
>> As for v2, I'm omitting "VMX: correct PDPTE load checks" from v3, as I
>> can't currently find enough time to carry out the requested further
>> rework.
> Andrew, George?
You've not fixed anything from my concerns with v1.
This doesn't behave like real hardware, and definitely doesn't behave as
named - "struct hvmemul_cache" is simply false. If it were named
hvmemul_psc (or some other variation on Paging Structure Cache) then it
wouldn't be so bad, as the individual levels do make more sense in that
context (not that it would make the behaviour any closer to how hardware
actually works).
I'm also not overly happy with the conditional nature of the caching, or
that it isn't a transparent read-through cache. This leads to a large
amount of boilerplate code for every user.
~Andrew
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