Re: [Xen-devel] [PATCH] tools/pvh: set coherent MTRR state for all vCPUs

[Wei Liu <wei.liu2@xxxxxxxxxx>]

On Tue, Oct 02, 2018 at 06:36:14PM +0200, Roger Pau Monne wrote:
> Instead of just doing it for the BSP. This requires storing the
> maximum number of possible vCPUs in xc_dom_image.
> 
> This has been a latent bug so far because PVH doesn't yet support
> pci-passthrough, so the effective memory cache attribute is forced to
> WB by the hypervisor. Note also that even without this in place vCPU#0
> is preferred in certain scenarios in order to calculate the memory
> cache attributes.
> 
> Reported-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
[...]
> ---
> diff --git a/tools/libxl/libxl_dom.c b/tools/libxl/libxl_dom.c
> index 8a8a32c699..5c80aab767 100644
> --- a/tools/libxl/libxl_dom.c
> +++ b/tools/libxl/libxl_dom.c
> @@ -803,6 +803,7 @@ int libxl__build_pv(libxl__gc *gc, uint32_t domid,
>      dom->xenstore_evtchn = state->store_port;
>      dom->xenstore_domid = state->store_domid;
>      dom->claim_enabled = libxl_defbool_val(info->claim_mode);
> +    dom->nr_vcpus = info->max_vcpus;

This isn't strictly needed, but I think setting it for PV as well is
more consistent.


Acked-by: Wei Liu <wei.liu2@xxxxxxxxxx>

Andrew, can you give this a try?

Wei.

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