[Xen-devel] [PATCH v2 7/7] amd/pvh: enable ACPI C1E disable quirk on PVH Dom0

[Roger Pau Monne <roger.pau@xxxxxxxxxx>]

PV Dom0 has a quirk for some AMD processors, where enabling ACPI can
also enable C1E mode. Apply the same workaround as done on PV for a
PVH Dom0, which consist on trapping accesses to the SMI command IO
port and disabling C1E if ACPI is enabled.

Reported-by: Jan Beulich <jbeulich@xxxxxxxx>
Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
---
Cc: Jan Beulich <jbeulich@xxxxxxxx>
Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Cc: Wei Liu <wei.liu2@xxxxxxxxxx>
Cc: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
Cc: Brian Woods <brian.woods@xxxxxxx>
---
 xen/arch/x86/cpu/amd.c     | 13 +++++++++----
 xen/arch/x86/dom0_build.c  | 14 ++++++++++----
 xen/arch/x86/hvm/svm/svm.c | 21 +++++++++++++++++++++
 xen/include/asm-x86/amd.h  |  3 +++
 4 files changed, 43 insertions(+), 8 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index c394c1c2ec..18a9e92b3c 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -44,6 +44,9 @@ integer_param("cpuid_mask_thermal_ecx", 
opt_cpuid_mask_thermal_ecx);
 s8 __read_mostly opt_allow_unsafe;
 boolean_param("allow_unsafe", opt_allow_unsafe);
 
+/* Signal whether the ACPI C1E quirk is required. */
+bool amd_acpi_c1e_quirk;
+
 static inline int rdmsr_amd_safe(unsigned int msr, unsigned int *lo,
                                 unsigned int *hi)
 {
@@ -427,7 +430,7 @@ static void disable_c1_ramping(void)
        }
 }
 
-static void disable_c1e(void *unused)
+void amd_disable_c1e(void *unused)
 {
        uint64_t msr_content;
 
@@ -447,7 +450,7 @@ static void check_disable_c1e(unsigned int port, u8 value)
 {
        /* C1E is sometimes enabled during entry to ACPI mode. */
        if ((port == acpi_smi_cmd) && (value == acpi_enable_value))
-               on_each_cpu(disable_c1e, NULL, 1);
+               on_each_cpu(amd_disable_c1e, NULL, 1);
 }
 
 /*
@@ -626,9 +629,11 @@ static void init_amd(struct cpuinfo_x86 *c)
        switch(c->x86)
        {
        case 0xf ... 0x17:
-               disable_c1e(NULL);
-               if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value))
+               amd_disable_c1e(NULL);
+               if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value)) {
                        pv_post_outb_hook = check_disable_c1e;
+                       amd_acpi_c1e_quirk = true;
+               }
                break;
        }
 
diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c
index 7b1aaaa7cb..eca0255a43 100644
--- a/xen/arch/x86/dom0_build.c
+++ b/xen/arch/x86/dom0_build.c
@@ -12,6 +12,7 @@
 #include <xen/sched-if.h>
 #include <xen/softirq.h>
 
+#include <asm/amd.h>
 #include <asm/dom0_build.h>
 #include <asm/guest.h>
 #include <asm/hpet.h>
@@ -442,10 +443,15 @@ int __init dom0_setup_permissions(struct domain *d)
     /* PCI configuration space (NB. 0xcf8 has special treatment). */
     rc |= ioports_deny_access(d, 0xcfc, 0xcff);
 #ifdef CONFIG_HVM
-    if ( is_hvm_domain(d) && opt_dom0_debug_ioport )
-        /* HVM debug console IO port. */
-        rc |= ioports_deny_access(d, XEN_HVM_DEBUGCONS_IOPORT,
-                                  XEN_HVM_DEBUGCONS_IOPORT);
+    if ( is_hvm_domain(d) )
+    {
+        if ( opt_dom0_debug_ioport )
+            /* HVM debug console IO port. */
+            rc |= ioports_deny_access(d, XEN_HVM_DEBUGCONS_IOPORT,
+                                      XEN_HVM_DEBUGCONS_IOPORT);
+        if ( amd_acpi_c1e_quirk )
+            rc |= ioports_deny_access(d, acpi_smi_cmd, acpi_smi_cmd);
+    }
 #endif
     /* Command-line I/O ranges. */
     process_dom0_ioports_disable(d);
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index dd0aca4f53..2ed24a624c 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -1272,6 +1272,24 @@ void svm_host_osvw_init()
     spin_unlock(&osvw_lock);
 }
 
+static int acpi_c1e_quirk(int dir, unsigned int port, unsigned int bytes,
+                          uint32_t *val)
+{
+    ASSERT(bytes == 1 && port == acpi_smi_cmd);
+
+    if ( dir == IOREQ_READ )
+    {
+        *val = inb(port);
+        return X86EMUL_OKAY;
+    }
+
+    outb(*val, port);
+    if ( *val == acpi_enable_value )
+       on_each_cpu(amd_disable_c1e, NULL, 1);
+
+    return X86EMUL_OKAY;
+}
+
 static int svm_domain_initialise(struct domain *d)
 {
     static const struct arch_csw csw = {
@@ -1284,6 +1302,9 @@ static int svm_domain_initialise(struct domain *d)
 
     svm_guest_osvw_init(d);
 
+    if ( amd_acpi_c1e_quirk )
+        register_portio_handler(d, acpi_smi_cmd, 1, acpi_c1e_quirk);
+
     return 0;
 }
 
diff --git a/xen/include/asm-x86/amd.h b/xen/include/asm-x86/amd.h
index e9867c7823..71fc52924e 100644
--- a/xen/include/asm-x86/amd.h
+++ b/xen/include/asm-x86/amd.h
@@ -148,4 +148,7 @@ extern s8 opt_allow_unsafe;
 void fam10h_check_enable_mmcfg(void);
 void check_enable_amd_mmconf_dmi(void);
 
+extern bool amd_acpi_c1e_quirk;
+void amd_disable_c1e(void *);
+
 #endif /* __AMD_H__ */
-- 
2.19.1


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