Re: [Xen-devel] [PATCH v3] arch/x86: Add registers to vm_event

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 18.10.18 at 11:02, <aisaila@xxxxxxxxxxxxxxx> wrote:
> --- a/xen/arch/x86/vm_event.c
> +++ b/xen/arch/x86/vm_event.c
> @@ -122,11 +122,60 @@ void vm_event_monitor_next_interrupt(struct vcpu *v)
>      v->arch.monitor.next_interrupt_enabled = true;
>  }
>  
> +static void vm_event_pack_segment_register(enum x86_segment segment,
> +                                           struct vm_event_regs_x86 *reg)
> +{
> +    struct segment_register seg;
> +
> +    hvm_get_segment_register(current, segment, &seg);
> +
> +    switch ( segment )
> +    {
> +    case x86_seg_ss:
> +        reg->ss.fields.base = seg.base;
> +        reg->ss.fields.limit = seg.g ? seg.limit >> 12 : seg.limit;
> +        reg->ss.fields.ar = seg.attr;
> +        reg->ss_sel = seg.sel;
> +        break;
> +    case x86_seg_fs:

Blank lines between individual case blocks please.

> +        reg->fs_base = seg.base;
> +        reg->fs.fields.limit = seg.g ? seg.limit >> 12 : seg.limit;
> +        reg->fs.fields.ar = seg.attr;
> +        reg->fs_sel = seg.sel;
> +        break;
> +    case x86_seg_gs:
> +        reg->gs_base = seg.base;
> +        reg->gs.fields.limit = seg.g ? seg.limit >> 12 : seg.limit;
> +        reg->gs.fields.ar = seg.attr;
> +        reg->gs_sel = seg.sel;
> +        break;
> +    case x86_seg_cs:
> +        reg->cs.fields.base = seg.base;
> +        reg->cs.fields.limit = seg.g ? seg.limit >> 12 : seg.limit;
> +        reg->cs.fields.ar = seg.attr;
> +        reg->cs_sel = seg.sel;
> +        break;
> +    case x86_seg_ds:
> +        reg->ds.fields.base = seg.base;
> +        reg->ds.fields.limit = seg.g ? seg.limit >> 12 : seg.limit;
> +        reg->ds.fields.ar = seg.attr;
> +        reg->ds_sel = seg.sel;
> +        break;
> +    case x86_seg_es:
> +        reg->es.fields.base = seg.base;
> +        reg->es.fields.limit = seg.g ? seg.limit >> 12 : seg.limit;
> +        reg->es.fields.ar = seg.attr;
> +        reg->es_sel = seg.sel;
> +        break;
> +    default:
> +        break;

Either add ASSERT_UNREACHABLE() or drop the default case.

> @@ -157,6 +157,19 @@
>  #define VM_EVENT_X86_CR4    2
>  #define VM_EVENT_X86_XCR0   3
>  
> +struct x86_selector_reg {
> +    union
> +    {
> +        uint64_t bytes;
> +        struct
> +        {
> +            uint32_t base;
> +            uint32_t limit  :    20;
> +            uint32_t ar     :    12;
> +        } fields;
> +    };
> +};

I don't understand why sel was moved out. Are you tight on
space here, such that you can't tolerate the padding bytes?

I also question the need for a union here. You don't use
.bytes anywhere afaics.

Finally - what meaning to the low (or high) 4 bits of "ar"
carry?

> @@ -193,7 +206,19 @@ struct vm_event_regs_x86 {
>      uint64_t msr_lstar;
>      uint64_t fs_base;
>      uint64_t gs_base;

You previously removed them, and I think that was correct.
The field in the union should be uint64_t. Right now you leave
fs.base and gs.base uninitialized.

Jan



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