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Re: [Xen-devel] Interrupt injection with ISR set on Intel hardware
- To: Jan Beulich <JBeulich@xxxxxxxx>, Jun Nakajima <jun.nakajima@xxxxxxxxx>, Kevin Tian <kevin.tian@xxxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Thu, 25 Oct 2018 14:02:16 +0100
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- Cc: xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Wei Liu <wei.liu2@xxxxxxxxxx>, Roger Pau Monne <roger.pau@xxxxxxxxxx>
- Delivery-date: Thu, 25 Oct 2018 13:02:52 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Openpgp: preference=signencrypt
On 25/10/18 13:51, Jan Beulich wrote:
>>>> On 15.10.18 at 14:06, <andrew.cooper3@xxxxxxxxxx> wrote:
>> From the debugging, we see that PPR/IRR/ISR appear to retain their state
>> across the mwait, and there is nothing in the manual which I can see
>> discussing the interaction of LAPIC state and C states.
> Is it perhaps a bad idea to go idle with an un-acked interrupt?
Most likely.
Then again, going idle with an un-acked line interrupt does appear to
work. It is only un-acked edge interrupts which appear to hit this issue.
Still - I'd prefer some guidance from the hardware folk as to what can
realistically be expected here.
> Quite possibly that's not something an ordinary OS would do.
This is definitely not something an ordinary OS would do during normal
operation. Xen suffers more than most other hypervisors because our
device drivers are in dom0.
That said, can't we just mask the line at the PIC/IO-APIC and forgo the
PEOI stack entirely? The more I think about how our interrupt handling
works, the more I think vastly over complicated.
~Andrew
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