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Re: [Xen-devel] [PATCH v2 1/2] x86/TSC: don't allow deadline timer to be used with unfixed errata
- To: Jan Beulich <JBeulich@xxxxxxxx>, xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Fri, 2 Nov 2018 18:34:48 +0000
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- Cc: Wei Liu <wei.liu2@xxxxxxxxxx>
- Delivery-date: Fri, 02 Nov 2018 18:35:08 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Openpgp: preference=signencrypt
On 02/11/18 16:40, Jan Beulich wrote:
> In preparation of writes to the TSC_ADJUST MSR, avoid the bad
> interaction of writes to it and the TSC_DEADLINE one. Presumably the
> original Linux commit bd9240a18e ("x86/apic: Add TSC_DEADLINE quirk due
> to errata") refers to e.g. KBW092. (Of course this is an issue also
> without us writing the TSC_ADJUST MSR, if instead firmware did already.
>
> The errata checking can't be put in init_apic_mappings() as Linux does,
> as that runs before we update microcode on the boot CPU. It needs to
> happen before consumers of tdt_enabled, i.e.
> - __setup_APIC_LVTT() <- setup_APIC_timer() <- setup_boot_APIC_clock()
> - <- calibrate_APIC_clock() <- setup_boot_APIC_clock()
> - setup_boot_APIC_clock()
> setup_boot_APIC_clock() gets called from smp_prepare_cpus(), which sits
> after microcode loading (note that calibrate_APIC_clock() gets called
> before setting tdt_enabled).
>
> Also add an MFENCE as per Linux commit 5d7c631d92 ("x86/apic: Serialize
> LVTT and TSC_DEADLINE writes"), but I see no reason to put a conditional
> around it.
>
> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
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