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Re: [Xen-devel] [PATCH v4 05/44] x86emul: support basic AVX512 moves


  • To: Jan Beulich <JBeulich@xxxxxxxx>
  • From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • Date: Wed, 14 Nov 2018 16:26:38 +0000
  • Autocrypt: addr=andrew.cooper3@xxxxxxxxxx; prefer-encrypt=mutual; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA==
  • Cc: George Dunlap <George.Dunlap@xxxxxxxxxxxxx>, xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Wei Liu <wei.liu2@xxxxxxxxxx>
  • Delivery-date: Wed, 14 Nov 2018 16:27:11 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
  • Openpgp: preference=signencrypt

On 14/11/2018 14:35, Jan Beulich wrote:
>>>> On 13.11.18 at 18:12, <andrew.cooper3@xxxxxxxxxx> wrote:
>> On 25/09/2018 14:28, Jan Beulich wrote:
>>> +#define avx512_vlen_check(lig) do { \
>>> +    switch ( evex.lr ) \
>>> +    { \
>>> +    default: \
>>> +        generate_exception(EXC_UD); \
>>> +    case 2: \
>>> +        break; \
>>> +    case 0: case 1: \
>>> +        if (!(lig)) \
>> if ( !(lig) )
> Oops. By now I've looked at this many dozen times, and I've
> never noticed the style issue.

It is amazing how you get used to the code when you stare at it for
weeks on end.  In this case however, I expect it might be easier to spot
if the \ were aligned on the RHS.  (I still find aligned \ far easier to
read.)

>
>>> @@ -3272,6 +3387,7 @@ x86_emulate(
>>>      b = ctxt->opcode;
>>>      d = state.desc;
>>>  #define state (&state)
>>> +    elem_bytes = 4 << evex.w;
>> evex.w isn't filled by this point, is it?  We only fill evex.lr in the
>> !evex_encoded() case AFAICT.
> Well, that's another bit of (pre-existing) trickery: When we decode
> these special prefixes (VEX, XOP, and EVEX) we first read the bytes
> into vex.raw[]. The code dealing with the EVEX case then copies
> the two vex.raw[] bytes into evex.raw[].

Oh - I was looking for that, but failed to spot it.  Where is that?

>  Thus the common fields
> (between the prefix encodings) are filled uniformly, and uses
> through vex are fine also for the EVEX case. I think this is better
> than littering around many ?: expressions.
>
> As an aside - if the above didn't work, none of the testing would
> have succeeded.

I hoped as much, but in the absence of finding any suitable code, I
though I'd ask.

>
>>> @@ -6348,6 +6521,41 @@ x86_emulate(
>>>          ASSERT(!state->simd_size);
>>>          break;
>>>  
>>> +    case X86EMUL_OPC_EVEX_66(0x0f, 0x6e): /* vmov{d,q} r/m,xmm */
>>> +    case X86EMUL_OPC_EVEX_66(0x0f, 0x7e): /* vmov{d,q} xmm,r/m */
>>> +        generate_exception_if((evex.lr || evex.opmsk || evex.br ||
>>> +                               evex.reg != 0xf || !evex.RX),
>> Are the inner brackets necessary?
> I'd be happy to drop them - I've put them there mostly for you,
> who you want whatever tool to properly deal with indentation on
> such wrapped lines. Since I don't know the exact rules that tool
> follows, I may have gone too far, but then again I think the
> resulting different indentation between the two lines above and
> the next line (holding the other macro argument) isn't unhelpful.

BSD style already specifies that function parameters are aligned
vertically after the (, so this case is fine without.

The problematic case is bare block continuations (especially on return
statements) where the BSD style is 4 spaces in from the outer block.

>
>>> @@ -8819,6 +9070,44 @@ x86_emulate(
>>>                                    !is_aligned(ea.mem.seg, ea.mem.off, 
>>> op_bytes,
>>>                                                ctxt, ops),
>>>                                    EXC_GP, 0);
>>> +
>>> +            if ( evex.br )
>>> +            {
>>> +                ASSERT((d & DstMask) != DstMem);
>>> +                op_bytes = elem_bytes;
>>> +            }
>>> +            if ( evex.opmsk )
>>> +            {
>>> +                ASSERT(!(op_bytes % elem_bytes));
>>> +                full = ~0ULL >> (64 - op_bytes / elem_bytes);
>> I think we want a path which checks elem_bytes != 0 which is
>> release-build safe.  This feels like an XSA waiting to happen.
> Nothing _ever_ sets (or should set) elem_bytes to zero, and it gets
> initialized to a non-zero value right in this patch. When writing this
> code I indeed did think about adding a check against zero, but I
> couldn't figure what half way sensible action (other than BUG()ing)
> I could take in that case. Yet BUG() is in no way better than hitting
> #DE on the division.

An { ASSERT_UNREACHABLE(); return X86_UNHANDLEABLE; } block would be
better than BUG(), because at least it won't crash a release
hypervisor.  (At least being unsigned division, we don't have the -1
case to worry about).

~Andrew

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