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Re: [Xen-devel] [PATCH v3] amd-iommu: remove page merging code

Ping? Can I get an ack or otherwise from an AMD maintainer please?


> -----Original Message-----
> From: Andrew Cooper
> Sent: 28 November 2018 10:41
> To: Paul Durrant <Paul.Durrant@xxxxxxxxxx>; xen-devel@xxxxxxxxxxxxxxxxxxxx
> Cc: Brian Woods <brian.woods@xxxxxxx>; Suravee Suthikulpanit
> <suravee.suthikulpanit@xxxxxxx>
> Subject: Re: [Xen-devel] [PATCH v3] amd-iommu: remove page merging code
> On 28/11/2018 09:55, Paul Durrant wrote:
> > The page merging logic makes use of bits 1-8 and bit 63 of a PTE, which
> > used to be specified as 'ignored'. However, bits 5 and 6 are now
> specified
> > as 'accessed' and 'dirty' bits and their use only remains safe as long
> as
> > the DTE 'Host Access Dirty' bits remain unused by Xen, or by hardware
> > before the domain starts running. (XSA-275 disabled the operation of the
> > code after domain creation completes).
> >
> > With the page merging logic present in its current form there are no
> spare
> > ignored bits in the PTE at all, but PV-IOMMU support will require at
> least
> > one spare bit to track which PTEs are added by hypercall.
> >
> > This patch removes the code, freeing up the remaining PTE ignored bits
> > for other use, including PV-IOMMU support, as well as significantly
> > simplifying and shortening the source by ~170 lines. There may be some
> > marginal performance cost (but none has been observed in manual testing
> > with a passed-through NVIDIA GPU) since higher order mappings will now
> be
> > ruled out until a mapping order parameter is passed to iommu_ops. That
> will
> > be dealt with by a subsequent patch though.
> >
> > Signed-off-by: Paul Durrant <paul.durrant@xxxxxxxxxx>
> Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
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