[Xen-devel] [PATCH] x86/cpuid: correct dependencies of post-SSE ISA extensions

["Jan Beulich" <JBeulich@xxxxxxxx>]

First of all a PCLMULQDQ dependency was missing entirely. Add it as well
as AESNI and SHA to SSE2, as all of them act on vectors of integers,
whereas plain SSE supports vectors of single precision floats only. This
is in line with how e.g. binutils and gcc treat them.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
TBD: On the same basis, SSE3, SSSE3 and SSE4A should probably also
depend on SSE2 rather than SSE. In fact making this a chain SSE -> SSE2
-> SSE3 -> { SSSE3, SSE4A } would probably be best, and get us in line
with both binutils and gcc. But I think I did suggest so when the
dependencies were introduced, and this wasn't liked for a reason I
forgot.

--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -196,11 +196,12 @@ def crunch_numbers(state):
         # instructions.  Several futher instruction sets are built on core
         # %XMM support, without specific inter-dependencies.  Additionally
         # AMD has a special mis-alignment sub-mode.
-        SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE,
-              AESNI, SHA],
+        SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE],
 
-        # SSE2 was re-specified as core instructions for 64bit.
-        SSE2: [LM],
+        # SSE2 was re-specified as core instructions for 64bit.  Also ISA
+        # extensions dealing with vectors of integers are added here rather
+        # than to SSE.
+        SSE2: [LM, AESNI, PCLMULQDQ, SHA],
 
         # SSE4.1 explicitly depends on SSE3 and SSSE3
         SSE3: [SSE4_1],





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