Re: [Xen-devel] [PATCH v3] x86/AMD: flush TLB after ucode update

["Woods, Brian" <Brian.Woods@xxxxxxx>]

On 1/28/19 8:25 AM, Andrew Cooper wrote:
> On 28/01/2019 14:19, Jan Beulich wrote:
>>>> --- a/xen/arch/x86/microcode_amd.c
>>>> +++ b/xen/arch/x86/microcode_amd.c
>>>> @@ -218,6 +218,12 @@ static int apply_microcode(unsigned int
>>>>   
>>>>       spin_unlock_irqrestore(&microcode_update_lock, flags);
>>>>   
>>>> +    /*
>>>> +     * Experimentally this helps with performance issues on at least 
>>>> certain
>>>> +     * Fam15 models.
>>> This is no longer experimental, now that we understand why.  How about:
>>>
>>> "Some processors leave the ucode blob mapping as UC after the update.
>>> Flush the mapping to regain normal cacheability" ?
>>>
>>> That way, its also slightly less cryptic in the code.
>> I did consider re-wording the comment, but decided to leave it unchanged,
>> for the way you word it not having public proof anywhere (for now at least).
>> I'm fine to change the comment, if I can explicit go-ahead from AMD. Brian,
>> Suravee?
> 
> Preferably with the amended wording, (but ultimately, as agreed upon
> with AMD), Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> 
Likewise,
Reviewed-by: Brian Woods <brian.woods@xxxxxxx>
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