Re: [Xen-devel] [PATCH 09/15] x86/pv: Add Hygon Dhyana support to emulate MSRs access

[Pu Wen <puwen@xxxxxxxx>]

On 2019/1/26 1:48, Jan Beulich wrote:
>>>> On 20.12.18 at 14:14, <puwen@xxxxxxxx> wrote:
>> The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and
>> counter MSRs, hardware configuration MSR, MMIO configuration base address
>> MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the
>> PV emulation infrastructure by using the code path of AMD.
>>
>> As hygon.c needs to write the load-store configuration(LS_CFG) MSR, so add
>> new case in write_msr to handle this situation.
> 
> Which hygon.c do you mean here? This addition, if valid at all, clearly

I mean hygon.c from the linux kernel. But in fact it's some other kernel
part will write LS_CFG MSR. So the description will be refined.

> needs its own patch and justification, the more that you permit access

This addition is needed, otherwise there will be warnings like:
"(XEN) emul-priv-op.c:1165:d0v12 Domain attempted WRMSR c0011020 from 
0x0206800000000000 to 0x0206800000000400"

Your suggestion is fine, will develop its own patch and justification in
next version patch set.

> (even if only for Dom0) on AMD as well.

As there will be the same warnings on AMD platforms, so I permit access
for AMD as well. I don't know if is this OK? If not, I'll permit access
for Hygon only.

-- 
Regards,
Pu Wen

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