Re: [Xen-devel] [PATCH] arm: gic-v3: clear GICR active interrupts

[Peng Fan <peng.fan@xxxxxxx>]

> -----Original Message-----
> From: Julien Grall [mailto:julien.grall@xxxxxxx]
> Sent: 2019年1月30日 21:49
> To: Peng Fan <peng.fan@xxxxxxx>; sstabellini@xxxxxxxxxx
> Cc: xen-devel@xxxxxxxxxxxxxxxxxxxx; Andre Przywara
> <andre.przywara@xxxxxxx>
> Subject: Re: [PATCH] arm: gic-v3: clear GICR active interrupts
> 
> Hi,
> 
> On 30/01/2019 13:36, Peng Fan wrote:
> >>> Each ICACTIVER0 registers hold the active bit for 32 interrupts.
> >>> However, this code assumes the register only hold 4 interrupts. So
> >>> this will write to unwanted area.
> >>>
> >>> There are only 16 SGIs, so it fits in one write to ICACTIVER0. As
> >>> wrote above, you also need to deactivate the PPIs. So the following
> >>> should
> >> be enough:
> >>>
> >>> /*
> >>>    * The activate state is unknown at boot, so make sure all SGIs
> >>> and PPIs
> >> are
> >>>    * de-activated.
> >>>    */
> >>> writel_relaxed(0xffffffff, GICD_RDIST_SGI_BASE + GICR_ICACTIVER0);
> >
> > Just have a following up question, according to
> > IHI0069D_gic_architecture_specification
> > "8.11.3 GICR_ICACTIVER0, Interrupt Clear-Active Register 0"
> > This field resets to a value that is architecturally UNKNOWN, Do we
> > need to take SPI into consideration as the following in gic_cpu_init?
> > for (i = 0; i < nr_lines; i +=32)
> >     writel_relaxed(0xffffffff, GICD_RDIST_SGI_BASE + GICR_ICACTIVER0 + (i
> > / 32) * 4);
> >
> > and move nr_lines out from gic_dist_init to a static global varaiable.
> 
> You can't clear SPIs through GICD_RDIST_SGI_BASE. You have to use the
> GICD.

Oops. I got wrong.

> 
> Furthermore, gic_cpu_init is called for every CPU so this is not a good place
> for clearing shared interrupts. Shared interrupts should be cleared in
> gic_dist_init as this is called only once.

Yes.

Thanks,
Peng.

> 
> Cheers,
> 
> --
> Julien Grall
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