Re: [Xen-devel] [PATCH] x86emul: correct AVX512BW write masking checks

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 30.01.19 at 20:04, <andrew.cooper3@xxxxxxxxxx> wrote:
> On 14/01/2019 11:40, Jan Beulich wrote:
>> For VPSADBW this likely was a result of bad copy-and-paste.
>>
>> For VPS{L,R}LDQ comment and code were not in line, but then again the
>> comment also wasn't fully updated from the AVX2 original it got cloned
>> from.
>>
>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
> 
> I'm guessing that these are covered by the first row of table 2-40, and
> the absense of {k1} in the instruction specifications?

Yes, that's how I understand it. I'm also generally taking binutils'
opcodes table as secondary reference, so see whether the Intel
folks having implemented that had any information differing from
what the SDM or the ISA extensions doc say. XED may also be
useful as a secondary source, but I think I didn't check it for the
cases here.

Besides the absence of {k1} it's also the absence of "under write
mask k1" in the description column, and the operation section not
describing conditional write back. I usually only take all three
matching up as sufficient proof for there not simply being an
omission somewhere.

Jan



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